SU446741A1 - Displacement sensor - Google Patents

Description

The invention relates to methods for receiving, transmitting and processing information and can be used in any industry that requires redundancy of the transmitted data.

The known device contains a comparator, a block of buffer memory, a block of supporting memory and storage of tolerances, a generator of address parcels.

When performing the task of reducing redundancy, this device gives a significant compression ratio only on gentle curves, and in areas with significant steepness it forms redundant data.

The purpose of the invention is to create a device that has a significant compression effect on both gentle and curved curves with significant steepness.

A signal analysis unit and an AND element are introduced into the device, the inputs of the signal analysis unit and the comparator are combined, another input of the signal analysis unit is connected to the second output of the comparator, and the output is connected to the buffer memory unit through the AND element. The third output of the comparator is connected to element I.

The drawing shows the block diagram of the device.

It contains a comparator 1, block 2 of the memory of tolerances; signal analysis unit 3;

logical element I 4, block 5 buffer memory, generator 6 address parcels. The device works as follows. Switched data is received at the V.chod of the comparator and the signal analysis unit. A sampling of channel 5, (i.e., 5g: / 2) is input into the comparator along with a predicted sampling value of 5.71 and a corresponding memory tolerance band. In the comparator, the valid sample is evaluated in accordance with the prediction made. If the prediction is not correct for this sample, the sample is directed to element I. At the same time, the Si / z sample is entered into signal analysis block 3, where by comparing with the previous sample 5.7i stored there, the rate of change of the voltage value D5g / 2 is formed, and then the value is compared with the rate of change of the value of the array during the broadcast period, i.e. A5i / i.

In the event that the result of this comparison goes beyond the established limit, a voltage pulse will arrive at the element P and the element AND will miss the signal about the value of the next sample, which then goes to the buffer memory block, where significant samples are stored at a non-constant rate. and converting them into notes of data with a constant tracking frequency. Therefore, to transfer the next

3

Sampling requires that two conditions be met: the output of the next sample from the tolerance band and the output of the ratio of the predicted rate of change of voltage to the current over the set limit.

If at least one of these conditions is not fulfilled, there will be no signal about the sample size, and at the next interrogation of the channel sensor Si, the sample Sf / a will go to room 1 and signal analysis unit 3 and all previously unrecorded operations will be repeated again. Comparator 1 will evaluate the fish sample Sj / 3 relative to the sampling corridor S {/ i, and in the signal analysis unit 3, D5g / h will be formed, which will then be compared with ASi / i.

These operations will be repeated until such time as the two conditions are met simultaneously. In the case of their execution, the next sample (for example, Si /) is entered into the buffer block of type 5 and at the same time the previous significant sample (for example, 5i / i) in the block of tolerance 2 and the signal analysis block 3 is erased and its place occupies and continues to be used as a reference value.

In addition, in the signal analysis unit 3, the rate of change of the voltage value ASi / i will be erased, and A5, / 4 will take its place, which later will also be used as a reference.

Subject invention

A device for measuring adaptation, which contains a comparator, the inputs of which are connected to the outputs of the block of tolerance values and the output of the generator of address slots, the other outputs of which are connected to the first inputs of the memory block of tolerances and the block of buffer memory, the first output of the comparator is connected to the second input memory unit of donor size, characterized in that, in order to expand the functionality of the device,

The signal analysis block and the logic element I are entered, and the inputs of the signal analysis block and the comparator are combined, another input of the signal analysis block is connected to the second comparator output, and the output through the element

And connected to the block of buffer memory, the third output of the comparator is connected to the element I.