SU830484A1 - Information compression device - Google Patents

Description

(54) DEVICE TO COMPRESS INFORMATION

I

The invention relates to telemetry and can be used in multi-channel digital telemetry systems for transmitting information with low redundancy.

A device for transmitting telemetry information is known, comprising a synchronizer, the output of which is connected to a channel switch, a full code memory block and, via an address coding block and a time coding block, to the first and second inputs of the buffer memory, the output of the channel switch is connected via a coding block to to the full codes memory block and to the signal analyzer, the output of the full codes memory block is connected to the signal analyzer, the output of which is connected respectively to the first input and through the block the memory of the increment codes to the second input of the increment code comparison block, the output of the full code memory block is connected to the input of the AND element, the output of the comparison block of the increment codes is connected to the second input of the AND element, to the input of the buffer storage device, the output of the AND element is connected to another input buffer store

device, and one output of the synchronizer is connected to the corresponding input of the memory block of the increment codes 1.

This device provides a high compression ratio, but is complex in its technical implementation and has a relatively low speed. The closest in technical essence to the present invention is a device comprising a switch, the control input of which is connected to a synchronization unit,

and the output through an analog-to-digital converter is connected to the block of buffer memory and to the first block of buffer memory and to the first block of comparison, which is connected via a synchronization block to the block of buffer memory. Unit output constant

the memory is connected to the information input of the adder, another information input of which is connected to the output of the analog-digital converter, the control input of the adder is connected to the output of the second comparison unit, another control input is connected to the output of the synchronization unit, and the output of the adder is connected to the input of the first comparison unit , while one information input of the second comparison unit is connected to the output of an analog-to-digital converter connected to the input of the storage unit, the output of which is connected to another input The second comparison unit, the control input of the second comparison unit is connected to the output of the synchronization unit, and the input of the synchronization unit is connected to the output of the second comparison unit 2. The disadvantage of this device is that the signal portions for which the module of the first derivative differs significantly from the coefficient B, processed with a low compression ratio. This reduces the overall compression ratio. This disadvantage is due to the fact that the process is extrapolated by the polynomials x (t) a ± b-t, where b const, i.e., straight with a constant angle of inclination. The purpose of the invention is to increase the compression ratio while maintaining the speed of the device. The goal is achieved by the fact that the device containing the switch, the information inputs of which are connected to the inputs of the device, the control input with the first output of the synchronization unit, the output with the input of the analog-digital converter, the buffer memory block, the output of which is connected to the output of the device, and an information processing channel including a permanent memory unit, an adder and a comparison unit, the output of the permanent memory unit is connected to. the first input of the adder, the output of which is connected to the first input of the comparison unit, the output of the analog-digital converter is connected to the combined first input of the buffer memory block and the second input of the adder, the third input of which is connected to the first output of the synchronization unit, the control unit and additional channels of information processing are entered , the first output of the control unit is connected to the second input of the buffer memory unit and the combined fourth inputs of the adders of all information processing channels, the second outputs of the control unit audio connected to the second inputs of the corresponding information processing channel comparing units, the third inputs of which are connected to the second output of the synchronization unit, and a fourth input - with the output of analog-to-digital converter, the comparison unit outputs connected to respective inputs of the control unit. The drawing shows the block diagram of the device. The device contains a switch 1, an analog-to-digital converter 2, a block 3 of buffer memory, a block 4 of control, a block 5 of synchronization, blocks of comparison, adders, blocks 8. | -8 fixed memory. Permanent memory blocks, adders and comparison blocks form N channels of information processing. N is selected based on a priori information about the process under investigation. The device works as follows. In blocks 8i-8c of the permanent memory, prior to the processing of the message, the values of the constant increments corresponding to each processing channel $ i biAt are added; i 1 ..., N, where D1 is the discrimination interval of the process under study; Bi-coefficient determining the increment of the predicted value along the i-th channel over one sampling interval. The coefficients b are determined from the a priori data about the process under investigation. The processing cycle of one sample consists of three cycles. On the first clock cycle, the contents of the constant memory blocks are added to the content of the corresponding adders 7.1-7. The second clock pulse from synchronization unit 5 processes the process through switch 1 to the input of analog-digital converter 2, where it is digitized. The resulting code is fed to the input of block 3 of the buffer memory, to the inputs of the comparison blocks and to the inputs of the adders. At the other inputs of the 6–6fj comparison units, the predicted process values (t) are received from the corresponding adders. On the third clock signal from the synchronization unit 5, the blocks 6i-6c compare the process values arriving at their inputs. If the actual value of the process X (t) differs from the value (t) predicted in the i-th channel by a value greater than the permissible absolute error, then the comparison unit 6 generates a signal signaling 6 that a substantial count has been detected in the i-M channel. Comparison results from each channel are transmitted to control unit 4. The control unit 4, analyzing the signals from the 6h-b comparison units, selects those channels in which a substantial count has been detected in the sampling interval under consideration. The comparison blocks of the selected channels from the control unit are given signals that block the further operation of these blocks. Thus, these channels are excluded from further signal processing. In addition, the control unit counts the number of channels that are turned off. If all channels are turned off at the sampling interval in question, the processing cycle is repeated. If, on this sampling interval, the last VC channel is turned off, the control unit generates a signal that allows unit 3 to

Claims (1)

Claim A device for compressing information containing a switch, the information inputs of which are connected to the inputs of the device, the control input is with the first output of the synchronization unit, the output is with the input of an analog-to-digital converter, the buffer memory block, the output of which is connected to the device’s ₅ output, and the processing channel information, including the read-only memory block, the adder and the comparison unit, the output of the read-only memory unit is connected to the first input of the adder, the output of which is connected to the first input of the comparison unit, you are ¹⁰ analog-to-digital move converter connected to the combined first input buffer memory unit and the second input of the adder, a third input coupled to the first output of the synchronization unit, characterized · ₁₅ scheesya in that, in order to increase the compression ratio, the apparatus entered the control unit and additional information processing channels, the first the output of the control unit is connected to the second input of the buffer memory unit and the combined fourth inputs of the adders of all information processing channels, the second outputs of the control unit are connected to the second input there are corresponding units for comparing information processing channels, the third inputs of which ₂₅ are connected to the second output of the synchronization unit, the fourth inputs are to the output of an analog-to-digital converter, the outputs of the comparison units are connected to the corresponding inputs of the control unit.