SU407301A1 - CONVERTER OF CODES FROM RESIDUAL SYSTEM OF CALCULATION TO POLYADIC - Google Patents

Description

I

The invention relates to the field of computer technology and is intended to convert codes defined in the number system of residual classes (SOC) into a polyadic system (into codes with mixed bases - CSR).

A known converter of the JUICE code into a polyadic number system, containing

yv

(LG-1) (Lg + 4)

+ 2 () -1)

2

l (N-2) (L-1)

modular summing and tabular schemes (where L is the number of modules SOK).

The proposed device is characterized in that each i-th parallel modular conversion channel contains (i-1) tabular modular addition schemes, the block for determining the residual quotient contains (N-2) modular addition tabular schemes (where L is the number of input code modules), and each modular addition tabular scheme contains a carry identifier, interchannel transfer formation logic, and two transcoding and convolution schemes, the first of which is connected to the outputs of the operand column decoder, and the outputs from the input E gates of the first group; the inputs of the second transcoding and convolution circuits are connected to the outputs of the aperrand row decoder, and the outputs to the inputs of the second group of valves; the inputs of the transfer identifier are connected to the inputs of the inter-channel transfer, and the outputs are connected to the inputs of the gates of the first group and the logic circuit of the formation of the inter-channel transfer, with the other inputs of which are connected to the outputs

the gates of the first and second groups and of both the transcoding and convolution schemes; the inputs of the table modular addition schemes corresponding to the k-th conversion level of the 1st parallel modular conversion channel are connected to the outputs of the table modular addition schemes corresponding to the (k-1) -th conversion level of the same channel; cross-channel outputs of tabular modular i-ro schemes

the channel is connected to the interchannel transfer inputs of the corresponding tabular modular addition schemes () of the first channel, the inputs of the first group of tabular schemes of the modular addition of the block for determining the remainder quotient are connected to the corresponding output code buses, and the outputs are connected to the inputs of the second group of tabular schemes for the modular addition of the same block. This simplifies the device and improves its speed. The device diagram for is shown in FIG. one; in fig. 2 shows a diagram of a tabular modular addition scheme, and FIG. 3 - timing diagrams for the operation of the device. The device contains (Fig. 1) table schemes 1-13 modular addition, where the table diagram 1 has inputs 14, 15 and outputs 16, 17 and forms the II parallel modular conversion channel (for module m-i). Tabular diagrams 2 and 7 have inputs 18, 19, outputs 20, -21 and inputs 22, 23, 24, outputs 25, 26, respectively, and form a third conversion channel (for module / C3). Tabular schemes 3, 4, 8 have inputs 27, 28, 29, outputs 30, 31; inputs 32, 33, outputs 34, 35; inputs 36, 37, 38, outputs 39, 40, respectively, the inputs OD, d / oo, OUTPUT oy, tu coition with I and form IV transform channel (for mod 4) Table 5-10 have Access 41, 42, 43; entry 44, 45, entry 46; entrances 47-50, exit 51; inputs 52, 53, 54, output 55, respectively, and form a V conversion channel (for module ms). Table schemes 11, 12, 13 have inputs 56, 57, output 58; inputs 59, 60, output 61; inputs 62, 63, output 64, respectively, and form a block for determining the remainder of the quotient (according to the first, for example, the even SOK module). Residual codes a, a, az, a, and JUICE are served on tires 65-69, respectively. The generated bits a3, 3, 3, a, QsKCO are removed from tires 70-74, respectively. The control signal buses (CAS) of the tabular modularization schemes in FIG. 1 not shown. Each modular addition table contains (Fig. 2) operand decoders for rows 75 and columns 76 (the received base square of the arithmetic table). ., with outputs 77 and 78, respectively, to which operand residues X and Y are fed to inputs 79 and 80, respectively; a transcoding and convolution circuit 81 with outputs 82 and 83, a transcoding circuit 84 and convolution with outputs 85 and 86; valve groups 87 and 88, keys 89, drivers 90; identifier of transfers 91, with inputs 92, 93 of inter-channel transfer and outputs 94, 95, 96; inter-channel transfer formation logic 97 with inter-channel transfer output 98; sampling matrix 99 with assembly circuits 100, a transformer array 101, switches 102, and read amplifiers 103; control signal bus 104. In the device operation description, the following formula symbols are adopted; nii - mutually simple modules of the engine SOK; i is the order number of the modules, ROC residues, and the values of the CSR bits; and; - residues of JUICE; Ø-value generated bits CSR; / - numbers of ROS residues involved in the formation of the t-ro value of CSR; ac - intermediate residual codes constituting the values of bits 6 of CSR for it and younger (i-1, ..., 1) modules of the system; Ar - output inter-channel transfer from this to the next module; Ag-1 is the input interchondial transfer from the previous to this module. According to the well-known algorithm, the values of the bits of the CSR are determined by a comparison:, / 0, 1.2 ..., g-1, 2 "o- + a11 F (a, a ,;,., I ,, ..., iA (i r :: const); Ar-1 -} -, iz, ii, iz {i The diagram of the actual converter for L (L1) contains 10 tabular modular addition schemes. Since the tabular schemes are two-operand, the members of the right-hand side for V The CSR bit can be grouped FF, for example, as follows: 05 Е 1 I (Os + th) + ("52 +" ") +" 54+ 41,. It follows that with a single use of each tabular scheme in the process conversion, maximum depth with V-5, it takes three Levels. A single use of two-table tabular schemes allows taking into account A | 0 input inter-channel transfer of Dg-i, d-2 ii directly when tabular sampling of the results of modular addition at the 2nd and 3rd conversion levels, and taking into account the main transfer Ai-i (overflow by this module) is carried out in each tabular scheme (except for the V module schemes) by logical formation of the output inter-channel transfer. Thus, the total number of links along the input inter-channel transfer for the V module channel reaches tp ex. The number of such links for IV and III modular channels is equal to 2 and 1, respectively. Table 1 of the converter implements the comparison: 02 Е I «2 + 2I t, 1 de .ii, and also forms the output inter-channel transport. Since the result of the addition is formed by the means of address sampling (addresses are the operand's transfer codes), it is possible to search for the sum and multiplication of the residuals of the constants t and q, simply by reconnecting the outputs of the operand decoders of the ablice scheme. Tables 2 and 7 implement the comparison: “WE I (o3 + 3i) + over + Ajm,) and form the inter-channel transfer of AZ AZ + Dz, where the indices“ 2 and ”7 mean the numbers of the table schemes. As in scheme 1, the outputs of the operand decoders of the tabular schemes 2 and 7 are reconnected for simultaneous multiplication by the constants | d ,, 11, On the corresponding residues. Tabular diagrams 3, 4 and 8 implement the comparison; "4 I (04 + a,} + (+ I ,,,) + Dz t, and form the inter-channel transport D L4 + A4 + D4. Operand decoders of the table circuits 3 and 4 with the interconnected outputs also multiply their residues on constants 1, 2 - Tabular schemes 5, 6, 9 and 10 implement the comparison ab Е I {(a, + «5,) + (052 + 053) 1 +« 54 + Д4 Im, Onerand decryptors of tabular schemes 5, 6 and 10 with reconnection outputs, the corresponding residues are also multiplied by the constants. H-Clause 4 An additional node for determining the residual quotient by the even (first) t; and numbers in the SOC for an even module, for example, tg 32, contains three tabular modular addition schemes, 12 and 13. From the definition of CSR with an accuracy to the integer part, we have: quotient | t,: | (oz-f) + (t-tz -a + t., - t ,, Table Schemes 11 and 12 with reconnected outputs of operand decoders to multiply the values of bits of the CSR, respectively, by t, and implement the sum of the expressions enclosed in parentheses. Scheme 13 forms the remainder of the quotient by the / P by the final summing of the output results of the tabular diagrams AND, and 12. Outputs 64 of the tabular schema 13 are connected to the residual code busses a. v, is equal to .V-1, and in (V-Pm channel forming UN-I -. Accordingly, the number of tabular schemes at the 1st 2nd conversion level in the channel / V-1 is equal to or one less than than in channel L, and the maximum value of inter-channel transfer to channel p Avna N-2. Hence the maximum number of links with input single inter-channel transport pertaining to any tabular scheme of the 2nd level will not exceed 2. The number of tabular schemes in the additional node that forms the quotient on an even module (or any first of (nj )}) equal to / V-2. The hardware by unmixing the actual tabular modular addition schemes was carried out on the basis of the complex use of the diagonal symmetry properties of arithmetic tables and their microstructural properties: the unambiguity of the mutual display of the sum of values between ropno arranged square tabular configurations, starting with a square base with a side of 2 or more operand values and insignificant volume unequal amount values within said square configurations. For mtSE2, the optimal side of the base square is 2 and the number of unequal places, with only 105 nodes of the modular addition table being implemented in a circuit, since it contains only 7 non-identical basic squares. Parallel to organizing the search for the node values of the modular arithmetic table in the group of unequal places of one base square and decoding of these places, depending on the numbers of groups of identical base squares that make up the table, almost double the performance of the tabular addition scheme. A modification of the well-known tabular scheme of modular addition, which is associated with the need to multiply the residual operands by the constants q and q ,, -, quickly taking into account the input inter-channel transfer D, and form a single output inter-channel transfer D; before the result of the addition is obtained as follows. The multiplication of operand residues X and Y, arriving at inputs 79 and 80 (Fig. 2), by the constants J.I and |, ii is realized by re-switching the outputs of operand decoders 75 and 76 in circuits 81 and 84, which decouple the residual O codes; into intermediate codes aij, with simultaneous convolution of the output spatial states of the complete decoder of the sample into decimal numbers of rows (columns) of the base square of the modular arithmetic table. At the same time, convolution and corresponding re-switching of code outputs 86 and 83 are performed by controlling the keys with 102 numbers of groups of basic squares. Accounting for input inter-channel transport b is performed by introducing a correction for the result of the modular addition, for which the number of, for example, the columns of the received base square is increased by a maximum value. Then, if you select the column and the row of the base square by the operand codes, you can simultaneously change the column number to + Ai-i and, by the properties of the modular addition table, obtain the identical increment of the result.

Inputs 92, 93 of the drip challah Al-i are associated with identifier 91, whose outputs 96 (Dg-1 0), 95 () and 94 (A, -i 2) are connected to the control inputs of the valve group 88; The corresponding output circuits 85 .circuit 84 are connected to the other inputs of the same valves, which excites (A + 1) -th or) -ro driver 90 (if kE driver must be selected with operand codes without taking into account the input transfer); these in the tabular scheme are increased by max (A, - i). The same maximum increment will be obtained by the number of inputs in the coordinate-node elements of the matrix of the sample 99, which determines the state number (for / n; 2 no longer 15, but 17 states) selected in the expanded base square. The tabular output interchannel transfer scheme is based on the property of the modular addition table, in which directly below the secondary diagonal are the sum residuals obtained by a single exception of the value of this module, which is taken into account as a single transfer to the next modular conversion channel. Accounting for each unit of input inter-channel transfer (from the previous modular channel) naturally causes a single shift down from the diagonal boundary between the regions of the 0th and 1st value of the output inter-channel transfer.

The logic circuitry 97 for generating the output inter-channel transport is an assembly of elements of the type AND-OR-NOT. Taking into account interchannel transfer in the final selection of the column of the expanded base square is reflected by the introduction of communication circuits between logic circuit 97 and the outputs of valve groups 87 and 88. The shift of the diagonal dial of the arithmetic table due to input interchannel non-transfer is implemented using the logic circuit 97 connections with the identifier transfers 91 through circuits 96, 95 and 94. Output 98 is used to connect logic circuit 97 to one of the inputs 92, 93 of identifier 91 in the table of the next modular channel.

 The process of integer conversion from the SOC to KCiQ is implemented in parallel over N modular channels (Fig. 1). Since the values of ui and Oi coincide, tabular charts in channel I (mi) are absent.

In order to reduce the delay in conversion, the operation of the device is organized with time compaction, taking into account the actual delays in the formation and passage of channel signals through cascade connections of tabular circuits.

Channel parallelism is provided under the condition that the interchannel transfer does not occur at the input of the corresponding tabular scheme simultaneously with the summed operands a, j. This is achieved by spacing in time the signals of the external synchronization of the converter, taking into account the delay in the formation of sums and interchannel transfers in tabular charts. In the converter itself (Fig. 1), the control signals of external synchronization are used, which follow at time intervals t (the delay in the formation of the output inter-channel transfer by the table diagram).

The timing diagram of the converter is shown in FIG. 3, where the leading edges of the pulses of the corresponding addition results are marked with solid lines, and the leading edges of the transfer pulses are marked with dotted lines.

Prior to and during the conversion to the CSR, the potentials of the codes of the residuals of the number being converted are maintained in dj, 02, 3 3, flb 55 (parallel static register).

The first and at the time tj are the III and V modular channels of the converter. In this case, the external control signal US: enters table schemes 2, 5, and 6, and operand inputs 18, 19, 41, 42, 44, and 45 are applied to the potentials of the residual codes a and az, Ci and as, az, and az. The next (through time t) signal US2 includes the modular channels of PI IV. The time t is sufficient so that by the time of launch of channel IV at the output 21 of scheme 2 of channel III a partial intercapalo

ny transfer az. By the time f4 - the beginning of the formation of the tabular scheme 1 at the output 16 of the code, the value of f2 - the potentials of partial sums and transfers are also set at the outputs 20, 43, 46, 30, respectively. 34 and 17, 31, 35 (Fig. 1, 3). At the moment of time ts table cuts 7-9 are started by the signal HMS, and at the moment t. signal US4 - tabular diagram 8. The start times of circuits 7 and 8 determine the beginning of the formation, respectively, at outputs 25 and 39 of codes a and 04,

7 with partial interchannel carry Az

output 26 is generated when circuit 8 starts up. At time 5, the sync signal of the USB module triggers circuit 10 of the modular channel V. At the same time, the partial transfer A4 potentials (from output 40 of circuit 8) and partial sum are set at its inputs 54 and 52 (from output 51 of circuit 9 ). By the time point 7, at the output 55 of the circuit 10, the code note potentials of the values hell appear and the conversion process ends. Thus, the total delay of the proposed converter from JUICE to CSR at is. The potentials of the codes al, d2, az, ui, as CSR, arriving at the respective fields, can be further memorized on a static register. The obtained values of the CSR bits are also used in the store division of the residual representation of the number A by the first SOC module (for example, even) to determine the residual private representation of L by this module: - using block 1 Wl from the diagrams and 12 and 13 (Fig. 1) applying at the time / at the signal USV to the And and 12 circuits, at their outputs 58 and 61 at the moment 9, codes of partial direction | a2 + mj-aslffZi Im -ms-a - -mz-tn -m -aslm 20 will be formed, respectively. The latter are added up to the moment 11 in the synchronized CSS / circuit 13, the output of which 64 forms the Tabular scheme of modular addition in the process of transformation functions as follows. The presence of the operand codes J and Y at inputs 30 and 79 and 80 leads to the corresponding active state of the decipherors 75 and 76 (Fig. 2), a potential appears at the only output of each of which. Through the diodes of transcoding circuits 81 and 84 and convolution of co-35 dv potentials, 82, 85 are fed to the inputs of the valve groups 87, 88, respectively. The potential of the PA output of one of the valves 88 occurs in the case of simultaneous influence of the control signal US along the circuit 40 104 and the potential of adjusting the result on the value of the input transfer along one of the circuits 96, 95 or 94. At the inputs of the keys 89, the starting potential appears when the match The US and the output potential of the circuit 81.45 acting on the circuit 82. The potentials triggering the selected key 89 and the driver 90 with their leading fronts also arrive at the inputs of the matching elements of the logic circuit 97 to form-50 interchannel transfer. The other inputs of the indicated coincidence elements, respectively, along the chains 86 and 83, through the 84 and 81 transcoding and convolution circuits, receive the output potentials of the decipherors 76 and 7555 and along the 96, 95, or 94 circuits from the identifier 91, the potential of the input interchannel transfer. The simultaneous influence of the indicated potentials on the inputs of the logic circuit 97 causes the appearance (through time t after 60 FP) on its output bus 98 of the generated signal of the inter-channel transfer output. At the same time, the potential at one of the areas 96, 95 or 94, corresponding to the value of the input inter-channel transfer "O, 25 or" 2, is previously generated by the matching circuits in the identifier 91 (from the output signals of the inter-channel transfer of the previous modular channel received by the inputs 92, 93 ). The output potentials of the recoding schemes and and convolutions of codes are received via code buses 86 and 83 groups of base squares of numbers to the input logic of keys 102. Thus, in parallel with the choice of key 89 and former 90, the key of the group of base squares with identical node values is also selected . At the output of the junction element of the matrix 99, common for the included circuits 89 and 90, a current pulse appears, and only one of the keys 102 to the common ground strip is pre-connected to one of the diodes of the assembly 100 connected to the output of the selected element of the matrix 99 , in only one of the code wires of the transformer line 101 will pass a pulsed current. The code signals of the thus selected tabular result of the modular addition from the secondary windings of the code transformers of the sticky strip 101 are received in parallel to the inputs of the read amplifiers 103, on the output slopes of which, after the time from the moment of the supply of the US, the formed code signals of the modular operation appear, The subject of the invention. A code converter from a residual number system to a polyadic, containing a block for determining the quotient and parallel modular channels, is transformed. made on tabular modular schemes, each of which contains row and column operand decryptors, a sampling matrix with assembly schemes, a transformer line, read amplifiers and keys, drivers that are connected to the outputs of the first group of gates, and outputs to the first group the inputs of the sampling matrix, the keys whose inputs are connected to the outputs of the valves of the second group, and the outputs with the second group of inputs of the sampling matrix, characterized in that, in order to simplify the device and increase it quickly each i-th parallel modular conversion channel contains (i-1) tabular modular addition schemes, the block for determining the residual quotient contains (N-2) tabular modular addition schemes (where LH is the number of input code modules), and each modular tabular diagram addition contains the identifier of transfers, the logic circuit for the formation of interchannel transfer and two transcoding and convolution schemes, the inputs of the first of which are connected to the outputs of the operand descriptor of columns, and the outputs - with the inputs of the first group of gates, the inputs to Ora scheme

transcoding and convolution are connected to the outputs of the operand row decoder, and the outputs are connected to the inputs of the second group of gates, the inputs of the transfer identifier are connected to the inputs of interchannel transfer, and the outputs are connected to the inputs of the gates of the first group and the logic circuit for the formation of interchannel transfer; the first and second groups and both recoding and convolution schemes, the inputs of the tabular modular addition schemes corresponding to the 1 st transform level of the i-th parallel modular channel conversion, connected to the output 407301

12

mi tabular schemes of modular addition, corresponding to the (k-1) level of conversion of the same channel, the outputs of interchannel transfers of tabular schemes of modular

adding the t-ro channel are connected to the inter-channel carry inputs of the corresponding tabular modular addition schemes (f-j-l) -ro channel, the inputs of the first group of tabular modular addition schemes

the definitions of the residual quotient are connected to the corresponding output code, and the outputs are connected to the inputs of the second group of tabular modular addition schemes of the same block.

c, b .. ai66 741 H hi- 56 57 59 60 FIG. Si T / l (rig 2