SU374585A1 - - Google Patents

Description

one

The invention relates to specialized computer equipment designed to generate random numbers with a normal distribution law.

In known devices, the formation of uniformly distributed random numbers (DMC), in which the output numbers are successively removed one after the other, are used.

If it is necessary to form a normally distributed random number (NFS), it is required to use a digital computer (DVM), which successively one after another sums these uniformly distributed numbers to obtain one normally distributed number.

The aim of the present invention is to create an autonomous sensor of normally distributed random numbers (DDNS), which produces an NFC without a digital computer, which reduces equipment and time for obtaining an NFC.

This goal is achieved by the fact that a set of PDCs from a random number sensor (containing random sequence formers with a noise generator, a valve and a trigger, combining nodes with four inputs, each containing two joint schemes, the inputs of which are connected to the inputs of the collecting circuit, and combining are combined into a matrix, one of the rows and one of the columns of which are formed by random sequence generators, with two inputs of different matching schemes of any matching node connected to the corresponding the driver in the column) is fed to the inputs of the NSP decoder consisting of several stages of decoding the PCCH iodine transfer-through scheme, and the outputs

transfers of any bit of the zero level of decryption are connected to the inputs of several leading bits of the first stage of decryption, the outputs of transfers of any bit of the first stage to the inputs of several high bits of the second stage, etc., to the last stage whose outputs are connected to the end-to-end transfer scheme; at the same time, the inputs of the twofold bit of the decoder are connected to the outputs of all the first bits

the matrix of nodes combining the random number sensor, the inputs of the second digit of the decimator - to the outputs of all the second bits of the matrix, etc., up to the last stage. In the descrambler a simultaneous conversion is performed.

of this set of numbers in one nsc.

The block diagram of the device is presented in FIG. one.

From the registers of random sequence formers (FSP) 1 and 2 random

Sequences are fed to a matrix of 3 nodes of combining, in which of these sequences are formed L / n-bit RS (PC4i, PCB, ..., PCP). from the outputs of matrix 3, these numbers are fed to the inputs of the decoder 4, in which the set of DMC is converted to one NSP.

A decoder is used in the decoder in multi-code.

The principle of operation of the decoder is as follows. With simultaneous summation (conversion) of the terms of the SRP. On the decoder, there is a gradual formation of transfer from the j-th bit of the J-th stage not only in the (/ + 1) -th bit of the (r + D) -th stage, as in the usual summation two or three terms, and at once in several senior bits.

The progressive formation of transfers ends in the last stage of deciphering, in which the number of exits in any category does not exceed two. The last step, as in the usual summation, is followed by the end-to-end transfer scheme (MTP).

FIG. 2 shows a functional diagram of the decoder for adding six five-bit numbers.

The first bit of all six items (Ci, Cg, Cz, Sc, C, Ce) is fed to the input of the first digit of the zero-level decoder 4i, to the input of 42 - the 2nd bits of all six items, etc. t-th bit (in this example - m 5), to the inputs of which the m-bits of all p-terms are supplied (in our case, l 6).

 Numbers at the outputs of the bit decoders indicate the number of units at its input, in the presence of which a unit appears at a given output, for example, if at the input 4 ° five of the six terms will have unit values, then the units at the outputs "4 and "This decoder.

It should be noted that the equipment of bit decoders is drastically reduced when building them on multi-stroke elements.

As can be seen from the functional diagram in FIG. 2, the lion stage is the last, since the number of outputs in any bit of this stage e exceeds two. After this stage, the corresponding bits of the end-to-end transfer schemes {5h, 5, ..., 5) are properly bit-spaced out of the / -th bit Sj, bitwise, the transfer from the / -th bit PJ and the end-to-end transfer out of the i-th bit CHj. At the output of the SCS, a single code NSP is obtained.

 The last step is determined by successive logarithm of the number of terms at the input of each stage. So, for example, with the number, the terms n - 20 the last step will be the second.

Moreover, the logarithm is reduced to the nearest whole integer to the result.

The following is an example of the addition of six five-digit numbers in a multi-part code. As already noted, the last step with six terms is 1 step.

Example. Add up the following six typed numbers: 11111, 10101, 01001, 10010, 11011, 01010.

Addition table in multi code.

Check:

Note: The index above the number in the addition table indicates the bit number of the given stage, for which "one unit in this bit is remembered in mind.

Subject invention

A random number sensor containing random sequence formers, combining nodes combined into a matrix, one of which is vertical and one of the horizontal busbars of which are connected to random sequence formers, characterized in that in order to shorten the time for generating normally distributed ones. random numbers, s contains the decoder

Normally distributed random numbers with

intermediate decoders of the original

random numbers and end-to-end carry,

with the outputs of the transfers of each bit

previous intermediate decoder

connected to the inputs of the group of higher-order bits of the subsequent decipher, the outputs of the last intermediate decoder are connected to the inputs of the end-to-end transfer circuit, each group of discharge inputs of the decoder is connected to the outputs of the like digits of the matrix of overlapping nodes.

RSCP

fC4,

DMC,