SU373887A1 - PULSE COUNTER - Google Patents

Description

one

The invention relates to the field of automation and computer technology, in particular to forest devices on ferrite transistor cells. (

A pulse counter is known that is made on ferrite-transistor cells and contains iB each storage register register, transmission register and general fault control circuit.

However, the known counter does not have reliable performance.

In order to improve the reliability of the proposed counter, the ends of the write windings of the cells of the storage register of all bits, except for the first, are connected to the power source through the windings of the record of the first cells of the storage register of all previous bits, and the ends of the windings of the records of the cells of the storage register of the first bit, except the first cell and the end of the read winding of the first cell of the second storage register are connected to a fault monitoring circuit.

To simplify the fault check circuit, it is performed on a dynamic trigger with a common limiting resistor, in parallel with which a capacitive delay line is connected, and two auxiliary cells that are permanently magnetically opposite, and the outputs of the auxiliary cells and the input are set to O are connected to a power source through the windings of the quenching of the dynamic trigger cells, the input of which is connected to the input bus of the meter, and the output of the delay line is the output of the fault monitoring circuit.

The drawing shows an electrical diagram of the proposed meter.

The pulse counter contains the first, second, third and last bits / -4, respectively, the general circuit 5 of the fault control with output 6 and input 7 from the monitored cells of the first discharge, registers 5 and 5 of the storage and transmission of the first discharge and ferrite transistor cells 10-21.

The diagrams of all the bits of the counter are the same, therefore, using the example of the first bit, we consider the principle of operation of the device.

The iB cells 13–15 of the register 8 are used to store the unit in the intervals between the input pulses, the cells 10–12 of the register 9 serve to delay the pulse when the unit is transferred from one cell of the storage register 8 to the next. For this register cell 9, transmissions are constantly biassed to zero, although other modes are possible.

The "Setup in O" signal records the unit in the first cell 13 of the storage register 8, and all other cells in register 8 in the "O". The input signal reads all the cells of the storage register 8. Cell 13, located in "1", gives a pulse, which writes "1 to cell 10 of register 9 of the transmission. Cell 10, at the end of the cell / 3 pulse, writes “1 into cell 14” with its pulse. Similarly, with the following input signals, further movement of “1” to the cells of the storage register takes place. At the next input signal, the pulse from cell 15 is fed to the output of cell 12, which is simultaneously the output of the first bit.

The connection of bits between each other is characterized by the fact that in each bit, with the exception of the first one, the ends of the windings of the record of the unit cell of the storage register are interconnected and connected to the beginning of the winding of the record of the unit of the first cell of the storage register of the previous bit and the end of the winding of the record "1 first Cells 13 of the first-time storage register 8 are connected to a power source. Consequently, the ends of the write windings of the "1 storage registers of all bits, except for the first one, are connected to the power source through the write windings of the unit of the first cells of the storage registers of all younger bits. Such a connection provides the recording of "1 to the original first cells, for example, cells 13, 19, etc., of all lower-order storage registers from the pulse of the highest-order transfer register cell that performs the switching for a given input signal. If, for any reason, in the most advanced bit that performs switching for a given input signal, does not transfer “1 from one cell to the next, then to the initial cells of all lower order bits, including the first,“ 1 recorded.

Circuit 5 controls the pulses of all cells of the first-order transmit register.

To do this, it is connected to the input 7 of the counter and the ends obm0: write current "1 all I | Cell register 8, except for the first cell 13, and the end of the read winding" 1 first cell 19 of the second discharge register, connected in parallel.

With the counter working correctly, the malfunction control circuit 5 for each input signal to input 7 receives a pulse from

one of the cells of the transfer register of the first bit, and at output 6 there is no fault signal.

To simplify the control circuit 5, it can be performed on a dynamic trigger with a common limiting resistor, parallel to which a capacitive delay line is connected, and two auxiliary cells, which are constantly magnetically oppositely polarized. The outputs of these cells and the input "Setup in O" are connected to the power supply through the power windings of the cells of the dynamic trigger. The input of the latter is connected to the input bus of the counter, and the output of the delay line serves as the output of the control circuit 5.

In this way, the reliability of the device is greatly improved.

Subject invention

Claims (2)

1. The pulse counter, made on ferrite-transistor cells, containing in each bit of storage register, transfer register and general fault control scheme, characterized in that, in order to increase the reliability of operation, the ends of the write windings of the cells of the register of the storage of all bits, except for the first, are connected to the power source through the windings of the record of the first cells of the register , the storage of all the previous bits, and the ends of the windings of the recording of the cells of the storage register of the first discharge, in addition to the first cell, and the end of the winding of reading the first cell of the second-storage register is connected to a fault control circuit. 2. A pulse counter according to claim 1, characterized in that, in order to simplify the circuit fault monitoring, it is performed on a dynamic trigger with a common limiting resistor, in parallel with which a resistor-capacitive delay line is connected, and two auxiliary cells, which are constantly magnetically differently polarized, with the outputs of the auxiliary cells and the input "Installation in O connected to the power source through the windings cells a dynamic trigger whose input is connected to the input width of the meter, and the output of the delay line is the output of the fault control circuit. Installation 1 / Installation 5 About Ustronodka SO Installation 8 About Uapano1k60