SU446107A1 - Memory device - Google Patents

Description

one

The invention relates to the field of automation and computing.

A memory device containing a drive with numerical cells made on ferrite cores with a rectangular hysteresis loop, connected in pairs by coils of communication and stitched with readable address buses, bit write buses, and bit memory read keys connected respectively to an address sample block is known. , by bit current recorders and playback amplifiers, and by a bias width coupled to a DC source. However, the bias current flows through the bias bus all the time, which increases the power consumption, in particular, leads to the need to increase the amplitude of the read current pulse (to compensate for the effect of the bias current). The constant consumption of power across the bias bus causes the cube of the charger to heat up, which reduces the upper limit of operating temperatures. For normal operation of the numerical cells of the charger, the bias current is needed only in the recording cycle.

The purpose of the invention is to reduce the power consumption of the memory. This is achieved by successively inserting a valve circuit controlled by the driver

2

records "O. In this case, the bias current in the bias flows only in the recording cycle.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 -

the process of reading and writing information in the memory element.

The device contains a drive 1, divided into numerical lines 2, which in turn consist of numerical cells 3. In

The composition of each numerical cell includes a selective 4 and a memory 5 cores with a rectangular hysteresis loop, connected by a link 6. In addition, the charger includes readable address buses 7, a bus

8 bias, write bit buses 9, read bit buses 10, amplifiers And playbacks, trigger 12 registers 13 words with input buses 14, discharge valves 15, bit write current drivers 16,

address sampling unit 17 with input buses 18, control unit 19 with input buses 20, control driver 21, bias current gate 22, offset source 23. The device works as follows

(see Fig. 2).

Before accessing the memory, the core 5 is in the state + Fg or - Fg, depending on the content of information stored in it, and the core 4 is always at the point - Fg.

The appeal to the memory is made in two cycles and

starts by reading the information stored in it. The read / gp impulse translates the severchik 5 to the state + Fg, and the core 4 through the coil 6 - to the state “O (-Fg).

In the pulse recording cycle of the control unit 19, the control driver 21 starts up, which opens the bias current gate 22. At the same time, a bias current pulse (/ cm) flows in the storage bias of the storage ring, slowly reversing the core 4 to the initial state is Fg, and the core 5 remains in the state + Фг ("O), as the current in the connection coil 6 is insufficient for its remagnetization.

The recording of "1 is carried out by fast re-magnetization of the core 4 under the action of the discharge current / sp on the write bus 9. As a result of forced reversal of the core 4 under the action of the total current / zp - + / ohm, a current / s arises in the coil 6 of the connection, which is sufficient to switch the core 5 from the state + Fg to the state - Fg (from "O to" 1).

Subject invention

A storage device containing an accumulator with numerical cells made on ferrite cores with a rectangular hysteresis loop, connected in pairs with connection coils and stitched with address read buses, bit write buses, read bit buses, respectively, connected with an address sample block, bit formats recording current and playback amplifiers, and the bias bus, as well as a control unit, whose outputs are connected to the discharge current driver through the discharge valves, from In order to reduce power consumption, it contains a valve, the output of which is connected to the bias bus, and the input is connected to the output of the control driver, the input of which is connected to the corresponding output of the control unit.

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