SU628535A2 - Magnetic storage - Google Patents

Description

The invention relates to computing and can be used for multichannel counting with time division of channels and storing accumulated results, and, if necessary, as a standard storage device.

According to the main author. St. No. 568971 known magnetic storage device containing a memory matrix made on three-aperture fluxor-type cores from a material with a rectangular hysteresis loop stitched by write, read, mode and control buses of the output drivers of the respective currents, reader and local control device 1 .

However, the known device has limited functionality.

The purpose of the invention is to expand the field of application of the device by implementing the summation of the subtraction of unit values for the contents of any memory cell directly in the storage device.

For this, a bit switch, a valve block and a transfer memory trigger are introduced into the proposed device, the bit switch outputs are connected to the inputs of the bit current mode drivers, the valve inputs are connected to the number register, and the outputs are connected to the bit current recorders, installation inputs "I and" On the trigger transfer transfer transfer are connected respectively to the outputs of the OR and AND elements, and the outputs to the memory control unit.

The drawing shows a diagram of the proposed magnetic storage device.

The magnetic storage device comprises a storage unit 1, consisting of three-hole fluxor-type cores 2 made of a material with a rectangular hysteresis loop, with one outermost opening larger than the other two. The drive is stitched with windings of 3 samples, passing through large holes of cores, discharge windings of 4 modes passing through large openings of cores in one direction, and through central holes in the opposite direction, discharge windings of 5 recordings and output windings 6 passing through small extreme openings of cores;

In addition, the device contains the address sample current drivers 7, the inputs of which receive the address code and control signals, and the outputs are connected to the windings of 3 selectors, the bit drivers of mode currents 8 with input coincidence circuits 9, and their input from the output outputs the one switch 10, and the outputs of the formers 8 are with 4-mode discharge windings, the bit-drivers 1 write currents, the outputs of the latter are connected to the discharge windings 5 of the record, and the input from the output of the valve block 12, to the input of which The code of the written number from the register is 13. The output windings 6 are connected to the inputs of the playback amplifiers 14, the outputs of the transfer memory trigger 15 are connected to a storage control unit (not shown), the installation inputs "1 - to the output of the OR 6 element and the single increment supply circuit 17, and the installation input “O is with element 18, control inputs are received at its inputs.

The device operates in the counting mode as follows.

Before the next addition of the unit on the address code buses 19, the potential code of the address of the memory cell is present in potential form, to the contents of which it is necessary to add one. A single increment is received on the trigger input 15 and set-. The trigger is in the state "1. Then the low-order bit of the selected memory location is read to the register of the 13th. Reading only the younger bit is ensured by the operation of only one current mode driver, a single sigal of the discharge switch arrives at the input of this driver,

- If the read bit is zero, then the process of adding one ends at the first call. The inverted signal from the output of the OR 16 element, which allocates non-zero states of the number register is reset to "About trigger 15 and to the lower slot of the memory cell," 1x is recorded. This completes the "1" process.

If the read bit is equal to one, then the trigger 15 remains in the state "1. Thereby, the transfer to the next most significant bit is remembered. At this bit, the "O is the result of adding modulo 2 the value of the read bit and the one

increments. Next, the bit switch is transferred to the next state and the next priority bit is addressed. The process is repeated until the transfer transfer memory is switched to the state "O by the zero state of all triggers of the number register after the next readout, or until the bit switch gives the signal" Overflow - The device can be used for subtracting single increments without changing the operating part. It is only necessary to change the sequence of operation of the control device, namely, the trigger is reset in "O when the value is read, a bit equal to one, the memory element is written to" O and the subtraction process ends. If the value of the read bit is zero, the trigger remains in the state "1, a unit is written into the memory cell, and the bit switch is transferred to the next state.

Claims (1)

1. USSR author's certificate number 568971 cl. G II C P / 08, 17.09.75.