SU395900A1 - DYNAMIC MEMORY CELL ON MDP-TRANSISTORS - Google Patents

Description

one

The invention relates to computing and can be used to design digital data storage devices for operational storage devices.

Dynamic type memory cells for operational memory are known. However, they erase information.matsii when reading.

In order to save information when reading, the proposed cell contains a buffer transistor, the gate and the substrate of which are connected to the bottom sensor (capacitor, the drain is connected to the readout bus, the source is connected to the readout bus, ode.

FIG. 1 is the scheme of the proposed storage cell; in fig. 2 is a diagram reflecting the regeneration of the code in the proposed storage cell.

The cell consists of an information transistor /, write transistor 2, a storage capacitor 3. Clamps 4, 5 are address inputs, respectively, when writing and reading code, bus 6 is designed to write a code to a cell, bus 7 to read a code from a cell.

FIG. 2, cut storage cells (transistors 8-9, (Capacitor / 0), over the hell output circuit (transistors, I, 12, capacitor 13) and 1k feedback circuit (Tr. NZI1 M-17 capacitors, capacitors 18, 19) Terminals 20-23 are clock busses, 24 are power supply busses. The read and write signals go to inputs 25 and 26, respectively.

During the first clock pulse bus 20, the capacitor 13 is charged, since the read signal at input 26 is absent and the source voltage (relative to the common point) is equal to the supply voltage of the circuit. During the action on the bus 21 of the second clock pulse, the readout signal arriving at the input 26 lowers the source of the source of the transistor 8 to zero and the signal stored on the co-capacitor 10 creates a condition for the discharge of the capacitor 13. The charge from this capacitor during the third clock pulse input 22 is transferred to the capacitor 18 and then during the action of the fourth clock pulse at the input 23 to the capacitor 19. At the same time as the first clock pulse, the recording signal 25 opens the transistor 9 and the battery.

the capacitor 19 is transferred to the capacitor 10, restoring the original level to the latter.

The recording and reading of information in the memory offered and known cells are similar.

An invention

A Diramic cell on MDPtrandistors containing an information transistor, an iKOTOiporo gate and a switch that connects to the transistor and the transistor of the information transistor, which is connected between the drain and the substrate of the information transistor, has a separate pattern. that, in order to store information on reading, the cell contains a buffer transistor, a gate and a substrate, which are connected to a storage capacitor, one hundred to a code reading terminal, a source to an address read terminal.

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