SU1695339A1 - Device for readout of color graphic information - Google Patents

Abstract

The invention relates to automation and computing and can be used to enter color graphic information into a computer. The purpose of the invention is to expand the field of application by providing readout of information from a wide class of color images. The goal is achieved in a device for reading color graphic information containing a sweep drum with an image carrier attached to it, optically connected to an optical-electronic converter, the outputs of which are connected to the analog inputs of the unit and analog-to-digital converters, the control input of the optical-electronic converter is connected to the first output of the control unit, the synchronization pulse generator located on the shaft of the sweep drum, the output of the synchronization pulse generator and is connected to the first input of the control unit, in that it further comprises a block of serial code converters in parallel, first and second buffer registers, a trigger, first and second switches, and a computer interface block containing the first and second signal conditioners, five elements And, the OR element, the address decoder, the status register and the buffer memory element. 1 hp f-ly, 3 ill. J

Description

The invention relates to automation and computing and can be used to enter color graphic information into a computer.

The purpose of the invention is to expand the field of application by ensuring the reading of information from a wide class of color images.

FIG. 1 is a block diagram of a device for reading color graphic information; in fig. 2 is a control block diagram; in fig. 3 is a diagram of a computer interface unit.

A device for reading color graphic information (Fig. 1) contains a scanning drum 1 with a carrier 2 of an object image 2 attached to it, an opto-electronic converter

3 (with color separation system), generator

4 synchronization pulses, 5 analog-digital converters block, 6 color components encoder, control block 7, block 8 serial-to-parallel converters block containing n shift registers (8-1. 8-п), first 9 and second 10 buffer registers, trigger 11. block 12 interface with a computer, the first 13 and

ON H) SL CO

with

H)

second 14 switches. The output 15 connects the device to an external computer.

Analog-to-digital converter unit 5 includes three amplifiers 16-18, three sampling-storage nodes 19-21, and three analog-to-digital converters 22-24.

The control unit 7 (FIG. 2) constitutes the reference frequency generator 25, the first frequency divider 26, the AND element 27, the second frequency divider 28, the driver 29 of the signals, the switch 30, the And element 31 and the memory management unit 32, FIG. 2 also denotes inputs 33-35 and outputs 36-40 of block 7.

The computer interface unit 12 (Fig. 3) contains the first 41 and second 42 signal conditioners, the address decoder 43, the first element AND 44, the element OR 45, the second 46 and the third 47 elements AND, the state register 48, the buffer element 49 of the memory The fourth, 50th and fifth 51 elements And have information input 52, outputs 53-56, control input 57, synchronization input 58, group of outputs 59 and output 15 for communicating with a computer.

A development drum 1 with a carrier 2 attached to it, the image of an object is optically coupled with an optoelectronic converter 3 with a color separation system (not shown). The outputs of converter 3 are connected to the corresponding inputs of block 5 of analog-to-digital converters.

The control input of the optoelectronic converter 3 is connected to the first output 36 of the control unit 7, the first input 33 of which is connected to the output of the generator 4 of synchronization pulses located on the same shaft with the sweep drum 1. The first output 53 of the computer interface 12 is connected with the sample inputs of the first 9 and second 10 buffer registers and the reset input of the trigger 11, the installation input of which is connected to the write inputs of the first 9 and second 10 buffer registers and to the third output 38 of the control unit 7, the first input 33 of which is connected to trigger output 11, Information input 52 of computer interface 12 is connected to the outputs of the first 9 and second 10 buffer registers, whose information inputs are connected to the outputs of the second switch 14 and the block 8 of serial-to-parallel code converters, respectively. The second group of information inputs of the second switch 14 is connected to the information inputs of the block 8 of serial code converters in parallel and the outputs of the color components of the encoder 6, and the first group of inputs of the second switch 14 is connected to the first group of inputs of the first switch 13 and the outputs of the analog-to-digital block 5

converters, the control input of which is connected to the fourth output 39 of the control unit 7, the second output 37 of the control unit 7 is connected to the control input of the block 8 of the serial code to parallel converters, and its fifth output 40 to the first control input of the color coder 6 constituents. The second input 35 of the control unit 7 is connected to the input 59 of the computer interface unit 12, the 5th output 56 of which is connected to the control inputs of the first 13 and second 14 switches and the third input 34 of the control unit 7.

The output of the first switch 13 is connected to the address input of the encoder 6 color components, the information input of which is connected to the third output of the computer interface unit 12. The fourth output of the block 12 is connected to the second group of information inputs of the pee switch 13, and its sixth output is the output 15 of the device.

The encoder 6 color components is a static-type random access memory. Trigger 11 is a common asynchronous trigger with split inputs (set and reset).

The control unit 7 (Fig. 2) is a logical machine of the combination type. The generator 25 of the reference frequency, generating a highly stable frequency, synchronizes the operation of all elements of the device for reading color graphic information. From the output of the first frequency divider 26, the frequency f arrives, the blocking of which by element 27 takes place at the signal of the beginning of the line, coming from the generator of 4 pulses

5 synchronization, while blocking the work of the entire device. Switch 30 performs, depending on the state of the signal on its control input, switching frequencies f and Vp depending on the mode of operation of the device, with the frequency / p being removed from the output of the second frequency divider 28. Depending on the selected mode of operation from the output of the element And 31 enters or does not receive the frequency

5 block 8 converters serial code to parallel. The memory management node 32 generates the necessary control signals for the static memory chips of the operational type, on which is implemented

encoder 6. The signals from the inputs 35 of the control unit 7, arriving at the inputs of the memory management node 32, determine the operating mode of the operational storage devices of the encoder 6 of the color components (writing or reading data). During the main operation mode, regardless of the state of the signals at the third and fourth inputs of the memory management node 32, the encoder 6 operates only in read mode.

The implementation of the computer interface unit 12 (Fig. 3) depends on the type of computational tools used and the possible interfaces of the device for reading graphic information with them. The first and second signal conditioners 41 and 42 serve to amplify the data bus and decouple signals from the minicomputer bus (not shown). The address decoder 43 samples the data of the access and use of the mini-computer. The state register 48 is software accessible from the side of the mini-computer by writing, and the buffer memory element 49 is programmatically accessible by reading. The element OR 45 and the elements AND 44, 46, 47, 50 and 51 serve to organize the necessary commutations (internal and external) with respect to the signal interface block 12.

The device works as follows.

The sweep drum 1 rotates to sweep along the line of the carrier 2 of the object attached to it. The opto-electronic converter 3, moving along the generator of the sweep drum 1, decomposes in rows. The optoelectronic converter 3 forms a probing luminous flux, which, reflected from the surface of the carrier 2 of the image of the object, is focused by the receiving optical system of the optoelectronic converter 3, whose color separation system splits it into three color-forming R-, G-, B- putters.

Three electrical signals are removed from the outputs of the optoelectronic converter 3, which are proportional to the luminous flux of the selected R, G, B components. These three electrical signals are fed to three amplifiers 16-18 blocks of 5 analog-to-digital converters, the gain factors of which are chosen so that they provide the optimal choice of dynamic ranges of blocks of post-processing of input signals. Analog signals are sampled by sampling-storage nodes 19-21,

the use of which is due to the requirement of providing the necessary dynamic error of the analog-digital converter 5, carried out by analog-digital converters 22-24.

The device operates in one of two modes: preparatory or mainly

0 depending on the state of the fifth output of the computer interface unit 12, which is controlled by the external computer.

The first 9 and second 10 buffer registers, as well as the trigger 11 and the generator 4 of the synchronization pulse5 are accessible by the computer through the computer interface unit 12 for reading, and in the encoder 6 the computer can both write data and read it.

Preparatory mode provides

0 the accumulation of the necessary number of statistical data to form the load table of the encoder 6, which is also filled in the preparatory mode. In this mode of operation, three numbers

5 which are the numerical equivalents of the luminous fluxes of the three color-forming R, G, B components related to one image element from the output of block 5 of analog-to-digital converters arrive through the first group of information inputs of the second switch 14 to the information input of the first buffer register 9. Pulses from the third output 38 of the control block 7, the follow-up period of which in this mode is equal to the sampling interval T j, data is recorded

in the first buffer register 9.

In the preparatory mode, a test (training) table is fastened to the scanning drum 1, consisting of the circumference of drum 1 separated by white borders along the circumference of the drum 1 in a specific sequence of color bands. Number

The 5 color bars are n-1, where n is the number of colors needed to distinguish, including white. Within a single band, all shades of the same color are present in the image of that type,

0 with which it is supposed to work, and all these shades will be assigned one color to color identification in connection with a finite number of definable colors.

4 clock pulse generator

5, during the period of rotation of the drum 1, a single start of the line is generated, for the duration of which the operation of the control block 7 and, consequently, of the entire device which does not set the ready flag for this time by changing the status of the trigger 11 is blocked. what

the external computer is fixed through the interface 12 when interrogating its state, the formation of digitized line images of the points readable on readiness begins. The end of the line is fixed by the arrival of the leading edge of the signal. The beginning of the line, during the complete revolution of drum 1, the computer receives information about the distribution of numbers within all color bands, the boundaries between which are determined by white lines, which correspond to the maximum for the selected analog-to-digital converter size. 22-24 numbers with some tolerance. The order of the computer color strips analyzed is known. In practice, one turn of the sweep drum 1 is not enough to create a load table of the random access memory of the encoder 6 color components, so you have to either increase the number of turns or adjust the hues of the colors in the bands to eliminate uncertainty. The result of the accumulation of static data of the preparatory mode of operation is the generation of a table function.

G | M1, where MBxfcZi; N S (MBX) N2, where Mext Z2; (1)

Mm / where Muxe Zm,

where Moss is the address of the random access memory, defined by the formula MVr ZR.2 ° + ZG 2L + ZB-22L, where ZR. ZG, ZB - numerical equivalents of dimension in L binary bits of the intensity of the light fluxes of the color forming R-, G-, B-components, is a generalizing parameter of the three-dimensional space Z (ZR, ZG, ZB);

N1, Nm - numbers of lanes on the test (training) table;

Zi, Zm are non-overlapping regions of the three-dimensional space Z;

m 2P - the number of colors distinguished by the encoder.

At the initialization stage of the preparatory mode of operation, you can see the zi, zm color codes Ki, Km, this procedure can be represented as a function mask Φ

 K, where MBX & ZI: КВых К, where l% t Zz: (2)

(k, where MBx fc Zm;

where Kvykh are the color codes from the palette in m definable components;

K - values of numerical codes from a numerical palette Ki, Km.

The peculiarity of this type of color initialization is that, by changing the appearance of the function F, it is possible to realize both the natural colorization and the acquisition of either a selective or blocking digital filter.

The result of the color initialization step is a function (2),

0The preparatory mode of operation is completed by loading the table-specified function Kvyh (Z) into the random access memory of the encoder 6, which is a two-input memory. When accessed

5 computers to the memory of the encoder 6 a signal arriving at the control input of the first switch 13 connects the address highway of the interface unit 12 to the address inputs of the encoder 6. To the data inputs

0 encoder 6 is connected to the data bus block 12 mate.

When the device operates in the main mode of operation, the signals that come in and the control inputs of the first 13 and second 14

5 switches, transmit to their outputs the signals arriving at the first group of information inputs of the switches. In this case, the numerical codes ZR, ZG, ZB, corresponding to each decomposition point of the image, are sent to the address inputs of the encoder 6. From the output of the latter, an n-bit code is recorded, which is written in n registers 8-1 to 8-n of the converter unit 8 sequential code

5 in parallel color code KOh. The frequency of the following pulses of shift registers 8-1 y 8-p is equal to f, their size is equal to R B (-),

where Y is the maximum possible bit depth

0 computer data words; E is the designation of the function that extracts the integer part of the argument.

The frequency of the write pulses in the second buffer register 10 and the pulses of the setting of the checkbox of the trigger 11 in

5 main operation mode is f / p.

The reading of the color codes P of consecutive points is made in the computer when the device is ready. In the main mode of the computer after the removal of the signal

At the beginning of the line, having read the first word of the data in readiness, it begins to form a numeric line of the digitized image from the segments of P consecutive pixels, stitching them.

5Expansion of the field of application of the device for reading color graphic information is achieved by allowing the creation of non-time-critical digital banks of geographical maps, both full-size and

functionally oriented (banks of heights, forests, waterways, as well as a network of roads and banks of geographical names) obtained from full-size maps by dialing or suppressing selected elements of a geographical map. As an informative attribute, their color features are used: the pure (steady) color of the element and the color gamut corresponding to the border areas (with a high color gradient).

Claims (2)

Claim 1. A device for reading color graphic information containing a scanning drum with an image carrier attached to it, optically coupled to an optical-electronic converter, the outputs of which are connected to analog inputs of an analog-to-digital converter unit, a control input of an optical-electronic converter connected to the first output of the control unit, the synchronization pulse generator, located on the shaft of the development drum, the output of the synchronization pulse generator from Connected to the first input of the control unit, an encoder of color components, characterized in that, in order to expand the field of application by providing information from a wide class of color images, it contains a block of converters of serial code into parallel, first and second buffer registers, trigger, first and second switches, and a computer interface unit, the first output of which is connected to the sample inputs of the first and second buffer registers and the trigger trigger input, the setup input of which is connected The recording inputs of the first and second buffer registers and the third output of the control unit, the second input of which is connected to the second output of the computer interface, the control input of which is connected to the output of the trigger, is connected to the outputs of the first and second computers. the buffer registers, the information input of the first buffer register is connected to the output of the second switch, the information inputs of the second buffer register are connected to the outputs of the block of serial-to-code converters The output coders of the color components coder are connected to the information inputs of the serial to parallel converter unit and the second group of information inputs of the second switch, the first group of information inputs of which are connected to the first group of information inputs of the first switch are connected to the outputs of the analog-to-digital 5 transducers, the control input of which is connected to the fourth output of the control unit, the second output of which is connected to the control input of the conversion unit in the parallel, fifth output of the control unit is connected to the first control input of the color component coder, the second control input of which is connected to the third output of the computer interface unit, the fourth output of which is connected to the second group of information inputs of the first switch whose control input, connected to the third input of the control unit, is connected to the fifth output of the computer interface unit and to the control input of the second switch, the output of the first switch is connected to and formational encoder input color components, and pa generato5 synchronization pulse output is connected to the clock input interface unit with a computer. 2. The device according to claim 1, characterized in that the interface to the computer 0 contains the first and second signal conditioners, five AND elements, an OR element, an address decoder, a status register and a buffer memory element, the first and second inputs of which are the synchronizing and control inputs of the block, the third input is connected to the output of the third element And, and the output is connected to the information input of the first signal conditioner and the information input of the block, the first 0 whose output is the output of the first element AND, the first input of which is connected to the output of the OR element, and the second input connected to the second input of the third element AND, the second input of the fifth element AND 5 and the control input of the first signal conditioner, is the signal input of the read device, the signal input of which is the control input of the second signal conditioner, connected to the second inputs of the second and fourth elements, the output of the first signal conditioner is connected to the information input of the second signal conditioner signals and to the input and output of the transmission 5 data of the device, whose address input is connected to the fourth output of the block and the information input of the address decoder, the first output of which is connected to the first input of the OR element, the second output to the first input of the second AND element, the third input to the first input of the third AND element, and the fourth output is to the second input of the OR element and the first inputs of the fourth and fifth AND elements, the output of the second signal conditioner is the third output of the block and is connected to the information input of the status register, the control input of which is connected The output of the second element is And, and the output is the fifth output of the block, the second output of which is the output of the fourth and fifth elements And, with the output of the third element And connected to the third input of the buffer memory element. /