SU596982A1 - Arrangement for displaying information on crt screen - Google Patents

Description

The device contains an analog-to-digital converter 1 input-signal block

2 sync, memory block 3, address 4 register, switch 5 codes, code conversion block 6, buffer register 7, and digital-to-analog converter 8.

The signal to be displayed is fed to an analog-to-digital converter 1 of the input signal, which converts the amplitude of this signal into a binary binary code (for example, a three-digit code, i.e., m 3). The output of this converter is included in n input groups of the switch 5 codes, and each of these n groups also includes m bits of the output word of memory block 3. The functional diagram shows, as an example, four groups of inputs for the switch of codes; thus, the word width of the memory block is equal to Fri 43 12. With the number of signal resolution elements, for example, 256x256, the number of memory cells is 256-256: 4 16000. The presence of several groups of inputs is determined by the ratio of the duration of the word recording cycle to the memory block. (for example, 0.8 microseconds) to the desired period of the digital-to-analog conversion of the output three-digit code, which usually corresponds to the band of the television video signal (for example, 0.2 microsecond, which corresponds to the frequency f 5 MHz). The control input V of the switch 5 codes is connected to the output of the synchronization unit 2. The outputs of the commutator 5 codes are connected to the inputs of the memory block 3; The outputs of the memory block 3 are also connected to the code conversion unit 6 and the buffer register 7. The output of the buffer register is connected to the input of the D / A converter 8, and the outputs of the code conversion unit 6 are connected to block inputs

3 connections, and this connection is disjunctively combined with the incoming signals from the switch output of the code switch. The code conversion unit 6 has an external control input W. The executive input C of this block and the control input Z (23) 1 of the buffer register 7 are connected to the outputs of the synchronization unit 2. The outputs of the synchronization unit are also connected to the input of the register 4 of the address, the output of which is connected to the address input of the memory unit 3 and the television sweep former.

The device operates as follows (for example, take 3 and p 4). The three-digit amplitude code of the input signal is applied to one of the four groups of inputs of the switch 5 codes. A three-digit code is fed to the same group of inputs — a part of the twelve-bit word from the output of the memory unit. The remaining nine bits of the word are sent to other groups of switch inputs, codes. The signal at the control input V of the switch 5 codes per output of this switch passes a 12-bit word as follows: the maximum of three-digit numbers sent to this group passes from one of the input groups (from the output of the analog-digital converter of the input signal from the output of the memory block), and the rest of the groups pass the code supplied from the memory block. Then, a 12-bit word is written from the output of the code switch to the memory block at the same address where the word was read from the memory to the input of the switch. This address and the number of the group of inputs in which the codes are compared are formed by the synchronization unit 2 and the address register 4 in accordance with the rectangular coordinates of the input signal. When the radar signal is displayed in rectangular coordinates, the azimuth - distance of the word address is directly determined by these coordinates, and when displayed in polar coordinates, a trigonometric transformation of these coordinates is required to determine the address.

In the address register 4, the address is also formed, respectively, the current rectangular coordinates of the television scan for reading the 12-bit word from the memory block to the buffer register 7. The signals at the control input of the buffer register comprise four groups of three-digit codes that make up this word, are sequentially supplied to a digital-to-analog converter 8 for indicating four signal samples along a television line. Then, the buffer register 7 reads the new word from the memory block.

In the address register 4, a sequence of addresses is also formed, by which the 12-bit word from the memory block is read into the four inputs of the code converter block 6. The signal at the executive input C of this block causes a reduction in the three-digit numbers constituting each of these words. The converted 12-bit word is written to the memory block at the same address at which the source word was read from the memory to block 6. This memory access may occur, for example, during the reverse horizontal line scan, but not about clearly on every line. If the number of memory cells is 16,000, and the memory is accessed on every second line, then one half-frame (i.e., for 312 lines and for a time of 20 milliseconds) will be viewed 312: 2 ft; 16Q memory cells, and all 16,000 cells will be scanned in 1600: 160 100 half-frames, i.e. during 1000.02 seconds 2 seconds. If during each reversal each of the four three-digit numbers decreases by one (the unit is not subtracted from zero), and the initial amplitude of the input radar signal was 7, then the afterglow time for this signal will be 2 seconds 7-14 seconds. When accessing the memory on each line, this time will be 7 seconds, and when accessing every fourth line it will be 28 seconds. When addressing two times on one line, this time will be 3.5 seconds.

Thus, with successive polling of the memory synchronized with the television scan, the number output from the memory through the buffer register 7 to the digital-to-analog converter 8 and the corresponding once-stored amplitude of the input radar signal will gradually decrease, causing a gradual decrease in the brightness of the mark whose television coordinates correspond to the radar coordinates of the signal. The duration of the afterglow is determined by the rate at which the words are read from

memory unit to code conversion unit 6, and this tempo can be regulated by external signals at control input W of unit 6. Resetting input signal 1 will not immediately reset the signal at the output of digital-analog converter 8, since when recirculating words from the memory through the switchboard of codes 5 they pass through the majorization schemes of m - bit codes (from the output of the analog-digital converter and the memory output) in each of the n groups of inputs of the switchboard of codes.

Claims (2)

1. US patent number 3.631.483, cl. 343-5. 2. Soloveychik I. Ye. Et al. Electronic information display devices in automated communication systems. “Holy Hour, 1973, p. 65. 1Na (transform the current / 1e & vn size current