SU1686600A1 - Device for symmetrization current in three-phase networks - Google Patents

Abstract

The invention relates to electrical engineering and can be used for automatic balancing of currents and compensation of reactive power in a three-wire three-phase circuit with time-varying parameters. The purpose of the invention is to expand the functionality by automatically compensating for reactive power, improving accuracy and speed. The device contains a filter 5

Description

The invention relates to electrical engineering and can be used for automatic balancing of currents and compensation of reactive power in a sin-conducting three-phase circuit with time-varying parameters.

The purpose of the invention is to expand the functionality by automatically compensating for reactive power, improving accuracy and speed.

Fig. 1 shows a block diagram of a device for balancing currents of three-phase networks; Fig. 2 is a functional block diagram of the control unit; on fig.Z - timing charts of his work.

Figure 1 shows the power source 1 and the three-phase load 2. In the general case, it is variable.

The device for balancing the currents of three-phase networks contains the sensor 3 of the RMS phase voltage, the switch 4 phase sequence, the filter of the symmetric components, the voltage ratio meter 6, the analog-to-digital converter (ADC) 7, the calculator 8 of the Fourier coefficients of the main harmonic, the buffer registers 9-11, accumulating adders 12-14, the executive body 15 of three adjustable reactive elements and the control unit 16,

A three-phase filter is connected to the three-phase network through a phase sequence switch 6, the output of which is connected to a point combining the first input (the input of the dividend) voltage ratio meter 6 and the first input of the control unit 16. A three-phase square sensor 3 is connected to the three-phase network. value of the phase voltage connected to the output of the second input (input divider) meter 6 ratio of voltages, the output of which is connected to the signal input of the ADC 7. Start input of the ADC 7 is connected to the first input of the unit 16 pack ION, and its information output - to the first (information) input calculator 8, the fundamental wave Fourier coefficient, second (control) input of which is connected to the second output of the control unit 16, and the third (control) input

combined with the control input of the phase sequence switch 4 and connected to the third output of the control unit 16. Three information (code) outputs of the calculator 8 coefficients

The main harmonic Fourier is connected to the information (code) inputs of the buffer registers 9-11, respectively, the control inputs of which are connected to the third, fourth and fifth outputs of the block.

10 controls The information (code) outputs of the buffer registers 9-11 are combined into a common bus and connected to the information (code) inputs of accumulating adders 12-14, and their sign outputs are connected to the second, third and fourth inputs of the control unit 16. Information (code) outputs accumulating adders 12-14 connected to the three information inputs of the Executive body 15, three

the output of which is connected to the phases of the network. The control inputs of accumulating adders 12-14 are connected to the seventh, eighth, and ninth outputs of control unit 16, and the inputs of the accumulator write

combined into a point connected to the tenth output of the control unit 16, the eleventh output of which is connected to the control input of the executive body 15.

The control unit 16 includes a frequency multiplier 17, a zero-body 18, triggers 19 and 20, delay element 21, element 2И 22, trigger 23, element ZI 24, trigger 25, element 2 OR 26, element 27 delay, pulse shaper 28 , Start button 29, pulse counter 30, delay element 31, trigger 32, delay element 33, ZILI element 34, pulse shaper 35, delay elements 36-39, triggers 40-42 and

a control pulse shaping unit 43 of the accumulating adders 12-14.

The first input of the control unit 16 is connected to the point that combines the inputs of the frequency multiplier 17 and the zero-body 18. The output of the frequency multiplier 17 is connected to the first input of element 2И 22, the second input of which is connected to the forward output of the trigger 23, and the output the input element of the delay element 21, the output of which serves as the first output of the control unit 16, or the second output of the control unit 16 and the input of the pulse counter 30.

The output of pulse counter 30 is connected to a point combining the counting input of trigger 20, the R input of trigger 23, the input of delay element 31, and the counting input of trigger 32, whose direct output is the third output of control unit 16. The output of the ZI element 24 is connected to a point that combines the S-input of the trigger 23 and the R-input of the trigger 25, which is connected to the output of the 2ILI element 26, connected by the first and second inputs to the outputs of the delay elements 31 and 27, by its S-input. The input of the delay element 27 is combined with the Reset bus and connected to the output of the pulse former 28, the input of which is connected to the point joining the Start button 29, the output of the delay element 36 and the eleventh output of the control unit 16. The direct output of the trigger 20 is connected to the S-input of the trigger 19, the inverse output of which is connected to the third input of the ZI element 24, connected by its first input to the direct output of the trigger 25, and the third input to the output of the zero-body 18 Direct output of the trigger 19 through the pulse shaper 35 is connected to a point combining the first input of the ZILI element 34, the input of the delay element 39 and S- input of the trigger 42. The output of the delay element 39 is connected to the point uniting the second input of the ZILI element 34, the input of the delay element 38, R- trigger input 42 and trigger input S-41. The delay element 38 is connected to a point that combines the third input of element 3 OR 34, the input of delay element 37, R-input trip PA 41 and S-input of trigger 40, whose R-input is connected to a point that connects the output of delay element 37 and input element 36 delay. The output of the ZILI element 34 through the element 33 of the delay is connected to the tenth output of the control unit 16. The direct outputs of the flip-flops 42, 41 and 40 are respectively the fourth, fifth and sixth outputs of the control unit 16, they are also connected to the first three inputs of the control-generating unit 43 of the control accumulating accumulators 12-14, the other three inputs of which are connected to the second, third and the fourth inputs of the control unit 16, and the three outputs of the control pulse shaping unit 43 of the accumulating adders serve as the seventh, eighth and ninth outputs of the control unit 16 5 Consider the operation of the proposed device

It is carried out in three stages. In the first stage, the quadratic component (Fourier coefficient) 1 (1) of the main component is measured.

0 current sequence harmonics, in the second stage, the in-phase and quadrature components (Fourier coefficients) l (2) x and l (2) v of the main harmonic of the negative sequence current are measured,

In the third stage, the conductivity codes bcc, bcc and bcc are formed, which are then entered into the executive body 15

In the initial state, the switch 4 phase sequence is set to one

0 of two states, in which a straight three-phase voltage sequence is applied to the 5 symmetric components filter and a voltage is allocated at its output proportional to the symmetric component

5 current l (i) of the direct sequence supplied to one input of the meter 6 voltage ratio and to the first input of the control unit 16 To the other input of the meter 6 voltage ratio comes from sensor 3

0 constant voltage proportional to the rms value of the phase voltage U At the output of the meter 6, a sinusoidal voltage is formed, the amplitude of which is proportional to the ratio i (i) / 3V. This voltage is applied to the signal input of the ADC 7, operating in standby mode. In the conversion mode, it is transferred at time tg by pulses arriving at its trigger input from

0 of the first output of the control unit 16 in the first and second measurement steps

The voltage from the filter output 5 symmetrical components through the first input of the control unit 16 is supplied to the inputs of the frequency knob 17 of the frequency 5 and the zero-body 18. The output of the frequency multiplier 17 forms a sequence of square pulses that are used to start the ADC 7 Multiplication factor multiply 0 l 17 frequency is chosen equal to n - the number of discretization points (or samples of instantaneous values) for the period of the voltage of a three-phase network. Thus, for the period of this voltage to the input of the launch of the ADC 7 will go p

5 start impulses. The voltage period is distinguished by the output pulses of the null organ 18, which are formed at the moments when the input voltage passes through one of the zeros, for example, from the negative to the positive region.

The measurement process, its first stage, begins by pressing the Start button 29. At the same time, at the output of the pulse former 28, a rectangular pulse is generated, which is fed through the reset circuit (installation) of all elements to the initial state. In particular, element 2I 22 and element ZI 24 in the control block 16 are closed by potentials of the flip-flops 23 and 25, respectively. On the third input, the element ZI 24 is opened by the potential of the trigger 19. Therefore, the pulses from the frequency multiplier 17 through the element 2I 22 and from the zero-body 18 through the element 24 is not passed from the direct output of the trigger 32 to the third output of the control unit 16 to the third input of the calculator 8 Fourier coefficients of the main harmonic, a signal is given that determines the computation mode of the quadrature component (Fourier coefficient) 1 (1) y.

The pulse from the output of the imaging unit 28 also enters through the delay element 27, which provides a delay of the start pulse with respect to the reset pulse, and through the element 2ILI 26 is applied to the S input of the trigger 25, putting it into the unit state. From the direct output of the trigger 25, the first input of the element ZI 24 receives the enabling signal, which is ready for the impulse to pass from the null organ 18 to the second input. The first impulse from the null organ 18 passes through the ZI element 24 and goes to the S input of the trigger 23 and to the R input of the trigger 25, returning it to its original state and thereby closing the ZI element 24 on the first input. The signal from the direct output of the trigger 23 opens element 2 and 22 on the second input, and pulses are transmitted from the frequency multiplier 17 to its output. These pulses go to the second output of the control unit 16 directly, to its first output through the delay element 21 and to the pulse counter 30, which they are summed up.

The signal from the second output of the control unit 16 is fed to the second input of the calculator 8 of the Fourier coefficients of the main harmonic, in which this signal sets the coso tq (q 1, n) codes previously recorded in the ROM of the calculator 8. With some delay required to complete the previous operations, the pulses from the frequency multiplier 17 at the first output of the control unit 16 are fed to the start-up input of the ADC 7, transferring it to the conversion mode at times tq (q ln). At times Tq, the instantaneous values of the input voltage of the ADC 7 are converted to codes proportional to i (i) q / 3V. These codes are given to the first, informational

input of calculator 8, in which

product codes N (i) cq

l (1) q sozoldd 3 V

by

all n discretization points tq and their algebraic summation is carried out. As a result, code is obtained in calculator 8

")with

 ;, tsUS05YCH JT) (C)

and

proportional to the quadrature component (Fourier coefficient) 1 (1) at the main harmonic of the current of the direct sequence. This code is written to buffer register 9.

After the n trigger pulses have arrived at the pulse counter 30 in the control block 16, a signal is generated at the output of this counter, with which it returns to the initial state. The same signal is fed to the counting input of the trigger 32, to the R input of the trigger 23 and through the delay element 31 and the element 2ILI 25 to the S input of the trigger 25. The trigger 32 is set to one state, the signal from its direct output goes through the third output control unit 16 to the switch 4 phase sequence and the third input of the calculator 8 Fourier coefficients of the main

harmonics. The phase sequence switch 4 is set to a different state, in which the voltage of the three-phase network is fed through it to the 5 symmetric components filter, but with a reverse

in order of phase rotation. The trigger 23 returns to its original, zero state, closing element 2 and 22 at the second input and stopping the passage of pulses from the frequency multiplier 17 to the first and second outputs of the control unit 16, which is necessary to synchronize the operation of the device with respect to the symmetrical component of the reverse sequence voltage allocated to the output of the filter 5 symmetric components. The delay time of element 31 is chosen longer than the transient time in this filter, so that the trigger 25, which specifies the beginning of the measurement cycle, is set to one.

after completion of transients in the device. The signal from the direct output of the trigger 25 turns off the element ZI 24 on the first input (on the third input it is opened by the signal from the inverse output of the trigger 19).

This ends the first stage and begins the second stage of measurement.

At the output of the filter 5, symmetric components stand out a voltage proportional to the symmetric component

a reverse sequence current 1 (2), which is fed to the input of the voltage ratio meter 6 and to the first input of the control unit 16. At the output of the meter 6, a sinusoidal voltage is formed, the amplitude of which is proportional to the ratio i (2) / 3V. This voltage is applied to the signal input of the ADC 7. The first pulse from the output of the null organ 18, which in the second measurement stage selects the transitions of the negative sequence component of the current through zero values from the negative to the positive region, passing through element 3 AND 22 to the second the input of the control unit 16 directly, to its first output through the delay element 21 and to the input of the pulse counter 30.

The operation of the device at the second stage is similar to its work at the first stage, the only difference is that the calculator 8 calculates both components (quadrature and in-phase or Fourier coefficients) of the main harmonic of the negative sequence current. In this mode of operation, the calculator 8 is transferred by a signal arriving at its third input from the third output of the control unit 16. In this case, the signals arriving at times tq from the second output of control unit 16 to the second input of calculator 8, define codes for both reference signals coscy tq and slnw tq (q 1, n), and for these codes and codes) q / 3V with ADC 7, codes are calculated in it

 (tia COSurtq I (, COSOrtq N (2) -N (2) sqrv (

which are algebraically summed over all n discretization points. As a result, codes are formed in calculator 8

N N "(") -sub "

("„ -2. -Vu 1

Guy-SP (QH-5 LIH ".

  -% LG1 "),

N

(their

AND

proportional to the in-phase 1p) x and quadrature 1 (2) y components (Fourier coefficients) of the fundamental harmonic of the negative sequence current. N (2) y and N (2) x codes are written to buffer registers 10 and 11, respectively.

At the same time, at the output of the pulse counter 30, a signal is again formed, which returns the counter 30 and the triggers 20, 23 and 32 to the initial state. The signal from the direct output of the trigger 20 arriving at the S input of the trigger 19, the latter is set to one state and by its signal from the inverse output blocks the element ZI 24 through the third input to pass the pulses from the zero organ 18. This completes the second stage and the third measurement stage begins. It is reduced to the algebraic summation of codes written in the buffer registers 9-11. in accumulating adders 12-14. It follows as follows.

The signal from the direct output of the flip-flop 19 is fed to the pulse shaper 35, at the output of which a short rectangular pulse is generated (Fig. 3a). This 5 pulse arrives at the S-trigger trigger 42, on a chain of series-connected delay elements 39, 38, 37 and 36, and through the ZILI element 34 to the delay element 33. Delay time of elements 39, 38, 37 and 36

0 equally, we denote it. It is chosen equal to twice the delay time of element 33. The time diagrams of the output pulses of delay elements 39, 38, and 37 are shown in FIG. 36, c, g

5, respectively. The output pulses of the elements 39 and 38 of the delay through the element ZILI 34 arrive at the element 33 of the delay. The time diagram of the output pulses of the element ZILI 34 is shown in

0 fig. Zd, and the output pulses of the element 33 delay - fig.Z. The pulse from the output of the imager 35, the passage in series through the elements 39, 38 and 47, alternately switches the triggers 42, 41 and 40, first in

5 single, and then to the zero state. At the same time, direct outputs of the flip-flops 42, 41 and 40 form control signals, the time diagrams of which are shown in Fig. Xe, g, g, respectively. These signals

0 are fed to the fourth, fifth and sixth outputs of control unit 16 to the control inputs of the buffer registers 9-11, connecting their information (code) outputs in series through the common bus to the information (code) inputs of accumulating adders 12-14. In addition, the signals from the direct outputs of the flip-flops 42, 41 and 40 are fed to the block 43 for generating the control pulses accumulating

0 adders, which are also fed to the second, third and fourth inputs of the control unit 16, signals from the sign outputs (bits) of the buffer registers 9-11. In block 43, signals are generated that are fed from the seventh, eighth, and ninth outputs of the control block 16 to the control inputs of accumulating adders 12-14, specifying their operation modes — summation or subtraction. After that, the output pulses of the delay element 33, arriving at the tenth output of the control unit 16, at the interconnected inputs of writing the accumulating adders 12-14, sequentially enter the code from each of the buffer registers 9-11 into the corresponding accumulating adders: N code ( i) y is entered into all three adders 12-14 for subtraction: code 1M (2) y - into adder 12 for summation with multiplication by two, and for adders 13 and 14 - for subtraction: code N (2) x - into adder 13 for subtraction, and for adder 14 - for summation. As a result, in the accumulating adders 12-14, the codes

NBC - 3- I ((2)

NCA - - I (1 +1 (2 + vTl (2;

NAB - -3-1 () y + T (2) y - (2) x;

proportional to the conductivity of the balancer. These codes, by a signal from the output of the delay element 36, arriving at the eleventh output of the control unit 16 to the control input of the executive body 15, are input to the executive body 15, where they affect the adjustable parameters of the symmetrizer.

The output pulse from the delay element 36 is also fed to the pulse generator 38 to automatically start the device and start a new balancing cycle.

Claims (1)

Apparatus of the Invention A device for balancing three-phase network currents, comprising a symmetric component filter, a mean square value of a phase voltage connected to one of the phases, a voltage ratio meter whose inputs are connected to the outputs of a mean square value of a phase voltage filter and filter symmetric components, as well as the executive body of three adjustable reactive elements connected to the linear voltage of a three-phase network, characterized in that, in order to widening of functionality due to automatic compensation of reactive power, increase of accuracy and speed, a phase sequence switch is inserted in it, which is connected between a three-phase network and a filter of symmetric components, an analog-digital converter, a calculator of Fourier coefficients of the main harmonic, three buffer registers, three accumulating adder and control unit with four inputs and eleven outputs, the output of the voltage ratio meter connected to the signal input of the analog-digital converter, the start input of which is connected to the first output of the control unit, the information output A / D converter is connected to the first input of the calculator of the Fourier coefficients of the main harmonic, the second input of which is connected to the second output of the control unit, its third input is combined with the control input of the phase sequence switch connected to the first input of the control unit, and connected to the third the output of the control unit, the three outputs of the coefficient calculator The 5th Fourier of the main harmonic is connected to the information inputs of the first, second, and third buffer registers, the control inputs of which are connected to the third, fourth, and fifth outputs of the control unit, the sign outputs of the buffer registers are connected to the second, third, and fourth inputs of the control unit, and the informational the outputs of the buffer registers are combined into a common bus and connected through it 5 to the information inputs of all three accumulating adders connected by their control inputs to the seventh, eighth and ninth outputs of the control unit, the recording inputs combined 0 among themselves, with the tenth output of the control unit and its outputs with the first, second and third information inputs of the executive body, whose control input is connected to the eleventh 5 to the output of the control unit, the control unit consisting of a frequency multiplier, a zero-organ, a pulse counter, two pulse shapers, a control pulse shaping unit 0 adders, eight triggers, element ZI, element 2I, element 2IL, element ZILI, eight delay elements and the Start button, while the inputs of the frequency multiplier and the zero-organ are combined into a point, 5 connected to the first input of the control unit, the output of the frequency multiplier is connected to the first input of element 2I, the second input of which is connected to the forward output of the first trigger, the output of element 2I is connected to a point joining the input of the first delay element connected by its output to the first output the control unit, the second output of the control unit and the input of the pulse counter, the output of which is connected to the point connecting the counting input of the second flip-flop, connected by its direct output to the third output of the control unit, zero input one of the first trigger, the counting input of the third trigger, connected by its direct output with a single the input of the fourth trigger, and the input of the second delay element connected to the output of the input element 2IL, the second input of which is connected to the single input of the fifth trigger through the third delay element and the first pulse shaper connected to the start button with a single input of the first trigger and connected to the output of the element ZI, connected by its first input with the direct output of the fifth trigger, the second input with the output of the zero-organ and the third input with the inverse output quarter the first trigger whose direct output through the second pulse shaper is connected to the point joining the first input of the ZIL element AND, the single input of the sixth trigger and the input of the fourth, fifth, sixth and seventh delay elements connected in series, the output of the fourth delay element is connected to the point combining the second input of the ZILI element, the zero input of the sixth trigger and the single input of the seventh trigger, the output of the fifth delay element is connected to the point joining the third input of the ZILI element, the zero input of the seventh trigger but and the single input of the eighth trigger, the output of the sixth delay element is connected to the zero input of the eighth trigger, the direct outputs of the sixth, seventh and eighth flip-flops are connected to the fourth, fifth, sixth 0 outputs of the control unit and to the first three inputs of the logic block for the formation of control pulses of accumulating adders, the other three inputs of which are connected to the second, third and fourth inputs of the block 5 controls, three outputs of the logic unit are connected to the seventh, eighth, ninth outputs of the control unit, which with its tenth output is connected via the eighth delay element to the output of the ZILI element, 0 and the eleventh output is connected to the point combining the output of the seventh delay element and the input of the first pulse shaper. From 5 K in K7 X6  4L / g # tfWft K12  kk Kf4 „From 9 and Ll Fig.Z