SU1689862A2 - Transducer of components of the first a c harmonic - Google Patents

Abstract

The invention relates to electrical measuring technique and allows to increase the speed of the measuring converter of the in-phase and quadrature components of the fundamental harmonic of an alternating non-sinusoidal current by reducing the sampling period. The in-phase and quadrature components are measured by digitally integrating the products of the current into the reference sine and cosine signals over a period using two reversible counters, the accumulation intervals of which are equal to the period of the measured current are shifted by half the period. At the end of each accumulation interval, the contents of the counters are written into the corresponding buffer registers with three-stable outputs connected to a common output bus. Since the moments of recording information in the buffer registers are shifted by half the period, therefore, the sampling period of the output signal is equal to half the period of the measured current, 1 sludge. (L

Description

The invention relates to electrical measuring equipment, is intended for use in automatic control systems of industrial electrical equipment, as well as in information and measuring systems for control and metering of electricity, and is an improvement of the converter according to the basic author. St. Ns 1485141

The purpose of the invention improve the accuracy and speed of the measuring transducer components of the main harmonic of alternating current

The drawing shows a functional diagram of the measuring transducer of the main harmonic components of the variable

The device includes a primary voltage converter 1, a primary current converter 2, functional converters 3 and 4, shapers 5 and 6 recording pulses, a low-pass filter 7, threshold element 8, multiplication blocks 9 and 10, shapers 11 and 12 of reset pulses, frequency multiplier 13 by n, voltage converters 14 and 15 - synchronous type frequency, T-flip-flops 16 and 17, frequency divider 18 by n / 2, two-input logic elements And 19-26, reversible counters 27-30 and buffer registers 31-34

In the proposed device, the input of the primary voltage converter 1 is connected to the potential input of the device, the input of the primary converter 2 of the current connection 00 4D 00

About GO

go

The device is connected to the output of the primary converter 1, and the output is connected to the combined control inputs of the functional converters 2 and 4, the low-pass filter 7, the frequency multiplier 13 and the frequency divider 18 2 are connected in series, the input of the low pass filter 7 is connected to the output of the primary converter 1, the output of the frequency multiplier 13 is connected to the combined control inputs of the function converters 3 and 4 and the combined clock To the inputs of converters 14 and 15 voltage-frequency of the synchronous type, the output of frequency divider 18 is connected to the combined inputs of T-flip-flops 16 and 17, the outputs of functional converters 3 and 4 are connected respectively to the first inputs of blocks 9 and 10 of the multiplication, the second inputs of which combined and connected to the output of the primary converter 2 current, and the outputs are connected respectively to the information inputs of the converters 14 and 15 voltage-frequency synchronous type, the output of the converter 14 voltage-frequency connected to the combined The second inputs of the two-input logic elements are And 19-22, the first inputs of the two-input elements And 19 and 21 are combined and connected to the direct output of the T-flip-flop 16, and the first inputs of the elements And 20 and 22 are combined and connected to the inverse of the T-flip-flop 16, the output of the voltage-frequency converter 15 is connected to the combined second inputs of two-input logic elements v 2j-2b, the first inputs of the And 23 and 25 elements are combined and connected to the forward output of the T-flip-flop 17, and the first inputs of the And 24 and 26 elements are combined v connected to the inverse output of the T-flip-flop 1 7, the outputs of the two-input logic elements And 19, 23, 21 and 25 are connected respectively to the summing inputs of the reversible counters 27,29,28 and 30, the outputs of the two-input elements And 20, 24, 22 and 26 are connected respectively to the subtractive inputs of the reversible counters 27,29 , 28 and 30, R-inputs of reversible counters 27 and 29 are combined and connected to the output of a reset puller 11, the input of which is connected to the output of a recording pulse generator 5, R-inputs of reversing counters 28 and 30 are combined and connected to the output of a reset puller 12 of pulses whose input is By connecting the output of the write pulse shaper 6, the inputs formers 5 and 6 write pulses

connected respectively to the direct and inverse outputs of the T-flip-flop 16, the information inputs of the buffer registers 31, 33, 32 and 34 are connected respectively to

the outputs of the reversible counters 27, 29, 28 and 30, the C inputs of the buffer registers 31 and 33 are combined and connected to the output of the driver 5 write pulses, the C inputs of the buffer registers 32 and 34 are combined and

connected to the output of the imager 6 write pulses, W-read inputs of the buffer registers 31 and 32, and connected respectively to the direct and inverse outputs of the T-flip-flop 16, L / -read inputs

buffer registers 33 and 34 are connected respectively to the direct and inverse outputs of the T-flip-flop 17.

The measuring transducer operates as follows.

Mains voltage

U UMslnu t,

where UM is the amplitude;

w- frequency

is fed to the input of the primary voltage converter 1, and from its output it is fed to the input of the threshold element 8 and the low-pass filter 7. In this case, the output signal

the threshold element has the form of a sequence of rectangular pulses

35

Ueh

Ue npnUi 0 (0 t T / 2) O at Ui 0 (T / 2 t T),

where Ue const is the voltage corresponding to the level of the logical unit.

Purpose of the filter 7 low frequencies

consists in suppressing high-frequency signals that are present, as a rule, in the voltage spectrum of an electrical network. The parameters of the lowpass filter 7 are chosen such that it does not introduce phase shift of the fundamental voltage harmonic. Thus, the output of the low pass filter 7 is a sinusoidal voltage.

50

and UM7 sin al.

The signal from the output of the low-pass filter 7 is fed to the input of the frequency multiplier 13 at n, at the output of which pulses U13 are formed, whose frequency is proportional to the frequency f of the supply network

fi3 nf n / T, (1)

where n is the transfer coefficient of the frequency multiplier 13;

P 2000, T-1 / f - the period of the network.

The pulses Ui3 from the output of the frequency multiplier 13 are fed to a frequency divider 18 by n / 2, at the output of which U18 pulses are generated with a frequency fia 2fi3 / n, which is equal to twice the frequency of the mains supply f (). The pulses from the output of the divider 18 frequency simultaneously arrive at the inputs of the T-flip-flop 16c by setting on a positive front and T-flip-flop 17c by setting on a negative front. As a result, a sequence of pulses Uie is formed at the output of the T-flip-flop 16, coinciding in phase with the signals U and Uy, and at the output of the T-flip-flop 17, a sequence of pulses U17 operates, shifted in phase relative to the signals of U and U by a quarter period. The pulses Uie from the direct output of the T-flip-flop 16 are fed to the serially connected driver of the 5 write pulses and driver of the 11 pulses of reset. At their outputs, at the beginning of each measurement period, determined by the output signal of the trigger 16 and, therefore, by the input voltage U, a successive short write pulse Us is formed. controlling the recording of information in the buffer registers 31 and 33, and a reset pulse Un, which ensures that the reversible counters 27 and 29 are set to the initial state.

Similarly, the pulses from the inverted output of the T-flip-flop 16 are fed to the sequentially connected shaper 6 write pulses and shaper 12 pulses of the reset, the outputs of which also generate short signals that allow you to respectively write information to the buffer registers 32 and 34 and set reversible counters to the initial state 28 and 30. The pulses UG and U12 are formed at the instant of time, i.e. shifted relative to the pulses of Us and Un by half a period.

Measured non-sinusoidal current

00

1 Ј (Mm m 1

sin (m sh t - -ft), (2)

where m is the harmonic number;

iMm is the amplitude of the m-th current harmonic;

tym phase shift of the m-th harmonic current,

converted by primary current converter 2 to voltage

U2 K2i,

(3)

where Ka is the transfer coefficient of the primary converter 2 current.

Functional converters 3 and 4 are digital shapers of quasi-harmonic reference signals (sinxjH | cosx |. Their operation is as follows. At times,

corresponding to the positive and negative edges of the pulses Us, i.e. at the moments corresponding to the beginning (t 0) and middle () of each voltage period, functional converters 3

and 4 is set by the output signal of the threshold element 8 Ua to the initial state. Next, functional converters 3 and 4 perform the conversion of the number of pulses Ui3,

coming from the output of the multiplier 13 frequency to their information inputs in kzazi-harmonic signals

 coif: U j / cosftt t /.

(4) (5)

As a result, the reference signals (4) and (5) are strictly synchronized with the mains voltage U, and their frequency coincides with the frequency of the network f.

Isolation of the in-phase component of the main harmonic of non-sinusoidal alternating current is as follows. Multiplication unit 9 performs multiplication of the signal U2. proportional to current, to the reference qualharmonic signal Us. As a result, on the output of the gun.

35

Ug K2K9i (t) | slnwn |.

(6)

where Kg is the transmission coefficient of the multiplication unit 9.

The signal Ug is fed to the input of voltage-frequency converter 14; and is converted by it to the pulse frequency fi4. The voltage-frequency converter 14 is a synchronous type device. The average value of its output

the frequencies are proportional to the input voltage Ug and the frequency of the clock pulses Ui3, coming from the output of the frequency multiplier 13:

50fl4 KMfl3 (U9 + UcM),

WITH)

where Ki4 is the voltage transfer coefficient of the voltage converter 14 is the frequency;

UCM - transducer bias voltage 14 voltage - frequency.

The purpose of the bias voltage UCM is to ensure the operation of the voltage-frequency converter with a two-pole

input signal. In this case, the DCM value is selected so that it is equal to or exceeds the maximum value of the module of the output voltage of the multiplication unit 9, i.e. UCM I Ugmax I.5

The output pulses of the voltage converter 14 are the frequency supplied to the second inputs of the two-input logic elements AND 19-22. The first inputs of the two-input logic elements AND 19 and 21 are connected to the forward output of the T-flip-flop 16, and the first inputs of the two-input logic elements And 20 and 22 are connected to the inverse output of the T-flip-flop. The outputs of the two-input logic elements And 19 and 21 are connected to the summing inputs, and the outputs of the two-input logic elements And 20 and 22 are connected respectively to the subtractive inputs of the reversing counters 27 and 28. At the beginning of each measurement period, the reversing counter 27 by the output pulse of the first driver 11 of the reset pulses is set to zero state. During the time interval at the direct output of the T-flip-flop 16, the signal of logical 1 acts, and the inverse signal of logical O. Consequently, the pulses from the output of the converter 14, the voltage — the frequency through the AND element 19 is fed to the summing input of the reversible counter 27. As a result, at the time instant, the number is recorded in the reversing counter 27

T / 2

N27 - Z Ul4 - / KMfi3 (Ug

0 t T / 2 o

Taking into account (1), (2), (3), (6) and catch Isin cot sin ft; t with

N is equal to

T / 2oo

Ni7 Ku / | 2K9sinon 245

 about -m 1

 iMm sin (m a) t - Vn) + CM dt.

During the second half period T / 2 t T, the forward output of T-flip-flop 16 is affected by a logical O signal, and the inverse logical signal 1. As a result, pulses from the output of the voltage-frequency converter 14 through the element 20 arrive at the subtracting input of the reversible counter 27. During the countdown time, the content of the up-down counter 27 decreases by

N27 Y

T / 2 1

U14

“/ Knfi3 (U9 + UCH) dt.

T / 2

Taking into account (1), (2), (3), (6) and (7) and the condition Isln O) t it at T / 2 t T the value of N 27 | equally

  K14Ј / -К2Kg Sin OL

1 T / 2

15 oo

 2 Mm s | n (man-type) + UcMJdt.

m 1

As a result, in time, 20 tons. at the end of the measurement period, in the reversible counter 27, a number is written in the binary complementary code

N27 N27 ™ Nl7 K2KgKi4 Ј 25

Tso

/ Sin tot Ј (Mm Sin (m ftJt - $ n) dt

om 1

thirty

one

 7j KgKdK-i P IMT COS 1 Ksf IMI COS, (8)

five

0

five

0

five

where KSF - K2KgKi4 n is the transmission coefficient of the measuring transducer over the in-phase channel, component.

At time t T, the output pulse of the write pulse generator 5 records the contents of the reversible counter 27 into the buffer ri-ri-page 31. Then, the output pulse of the reset pulse generator 11 is set to the zero state of the reversing counter 27.

At the time t T / 2, a short pulse is generated at the output of the pulse driver 6, which sets the reversible counter 28 to the zero state. During the time interval T / 2 t T at the direct output of the T-flip-flop 16, a logical O signal is applied, and the inverse output is a logical 1 signal. Therefore, the pulses from the output of the voltage-frequency converter 14 through the logical element And 22 are fed to the subtracting input reversible counter 28. As a result, at the moment of the reversible counter 28 write down the number

the trigger 17. The outputs of the elements 23 and 25 are connected to the summing inputs of the reversing 29 and 30, respectively, and the outputs of the elements 24 and 26 to the subtracting inputs of the reversing counters 29 and 30. At the beginning of each measurement period, the reversing counter 29 of the output pulses of the generator 11 of the reset pulses is set to zero state. During the time interval T / 4 at the direct output of the T-flip-flop 17, a logical O signal is applied, and the inverse signal is a logical one. Therefore, the pulses from the output of the voltage-current converter 15 are frequency through the And 24 element fed to the subtracting input of the reversible counter 29, where the counting of pulses occurs. As a result, at time t T / 4, in the reversible counter 29, the number is written in a binary HHTerfbHOM code

T / 4

N29 -Ј U15 "- / Ki5fl3

About t T / 1o

p T /

 (UlO + UCM) dt - K15 Ј /

about

with

К2Кю COS 0) 1 2 (tShH -

t 1

31 / 4CO

K15 $ / K2K10COSQM 2

1 1/4

  Mm

m 1

 sin (m ft) t - Y) + UCM dt.

During the time interval ZT / 4 t T at the direct output of T-flip-flop 17, a logical signal O acts, and the inverse signal of logical one 1. Therefore, in the reversible counter 29, a counting of pulses Uis occurs, during which its content changes by

t

N -Ј Uis - / Ki5fi3

ЗТ / 4 t тЗТ / 4

- (UlO + UCM) dt - Kl5 Ј /

1% / 4 oo

К2Кю cos ftH lMmsln (- 1 - t / .Vn) + UM dt.

Thus, at the point in time, i.e. at the end of the measurement period, in the reversible counter 29, the number in the binary additional code is written

- V-Vn) + UM dt

In this case, the sign of the recorded number is determined by the value of the high bit of the binary reversible counter 29 O, which corresponds to a positive value of the recorded number and 1 to a negative one.

During the time interval, the direct output of the T-flip-flop 17 is acted upon by a logical 1 signal, and the inverted signal is by a logical O. Therefore, the pulses from the output of the voltage-frequency converter 15 are fed to the summing input of the reversing counter 29. During the direct counting time 29 changes by

Nfe -XUis

T / 4 t 3T / 4

zt / 4 f Kisfi3 (Uio + UCM) dt

T / 4

3T / 4T / 4

 Kis - f KgKyu i cos p; t I Z

 T / 4m 1

- lMm sin (m (t) g - g / Au) + U-M dt

N29 N29 + MUS) + N

 -K2KioKis5 / cos SU t 2

 nm: 1

00

m

35

1mt sin (ft; mt -i / lm) dt КгкюК15 n 1 m, sin 1 Кхв1м1 sin Vi.

0

five

0

five

one

(ten)

where KQC 7: K2KioKis n is the transmission coefficient of the measuring transducer over the quadrature channel.

The quadrature component of the main harmonic of the alternating current is determined by the value of the high bit of the binary reversing counter 29. With a lagging current (-0), 1 is recorded as the highest bit, and the leading discharge (/ i 0) is recorded as O.

At the time, the output pulse of the write pulse generator 5 records the contents of the reversible counter 29 into the buffer register 33. Then, the output pulse of the reset pulse generator 11 sets the zero counter 29 to zero.

At the moment of time at the output of the formatter, 12 reset pulses form a N28 - 2 “

T / 2 t T

"/ KMf 13 (U9 + UCM) dt .5

T / 2

Subject to (1), (2), (3), (6) and (7) and subject to

lslnft) w t npwT / 2 t T the value of N 2c is equal to

N28 Ki4 $ / -K2Kgsln yt1 T / 2

00

 2 Mm Sln (mftJt - $ n) + CM

m 1

dt.

During the period of time T t ЗТ / 2 at the direct output of T-flip-flop 16, the signal of logical 1 acts, and at the inverse of logical O. As a result, the pulses from the output of the voltage-14 transducer 14 frequency through the logical element And 22 arrive at the summing input reversible counter 28. Over a period of time T t ST / 2, the contents of the counter are increased by

mIv 2 and ™ "

T t ST / 2

ЗТ / 2 / Kufi3 (Ug + UCM) dt.

Taking into account (1), (2), (3), (6) and (7) and the conditions is ln (i) l | tpriT tЈ 3 T / 2 the value of N as is equal to

ST / 2

N28 K14 / K2K9sln yf T T

00

 2 Mm sin (man - $ n) +,

m 1

As a result, at the moment of time, i.e. at the end of the measurement period, in the reversible counter 28 a number is written in the binary additional code

N28 - N28 + Nfe K2K9K14

ZT / 2oo

/ 2 Mm sin () dt

G / 2m 1

-I

 2 K KgKi4 n IMI cos t / Ji KSf IMI cos f). (9)

five

ten

15

0 5

0

five

0

five

0

five

At time t of the ST / 2, the output pulse of the write pulse generator 6 records the contents of the reversible counter 28 into the buffer register 32. Then, the output pulse of the reset pulse driver 12 is set to the zero state of the reverse counter 28.

Thus, the information is recorded in the buffer register 31 at the time, and in the buffer register 32 at the time. Information is issued on a common bus. In the time interval 0 t T / 2, the W-input of the buffer register 31 is acted upon by a logical 1 signal, and the W-read input of the buffer register 32 is a logical O. signal, therefore information on the common bus is output from the buffer register 31. In the time interval T / 2, the read input of the buffer register 31 is acted upon by a logical O signal, and the read input input of the buffer register 32 is a logical 1 signal, therefore the information is output from the buffer register 32.

Thus, the change of information on the bus, through which the code corresponding to the amplitude value of the in-phase component is transmitted, is performed twice during the period of the network, at times tr-0 and.

The quadrature component of the main harmonic of the alternating current is extracted in a similar manner. The multiplication unit 10 performs a multiplication of the signal U2, which is proportional to the current I, by a quasi-harmonic reference signal (J4. As a result, a signal is generated at the output of the multiplication unit

Uio K2Kiol (t) icosojt I,

where Kyu is the transmission coefficient of the multiplication unit 10.

The signal Uio is fed to the input of a voltage converter - frequency 15, at the output of which a sequence of pulses Ui5 is formed with a frequency

fl5 Kl5fl3 (UiO + UCM),

where KIS is the voltage-frequency converter transfer ratio 15. The output pulses of the voltage converter 15 are the frequency fed to the second inputs of two-gate logic elements AND 23-26. The first inputs of elements 23 and 25 are connected to the direct output of the T-trigger 17, and the first inputs of elements 24 and 26 to the inverse the Tets output pulse, which sets the reversible counter 30 to the zero state. During the time interval T / 2 t ЗТ / 4, the direct output of the T-flip-flop 17 is acted upon by a logical 1 signal, and the inverse by a logical O signal.

Consequently, the pulses from the output of the voltage-to-voltage converter 15 are fed through the logic element I 25 to the summing input of the reversible counter 30. As a result of the direct counting at time t ЗТ / 4, the number is recorded in the reversing counter 30

N30 2Uis "

T / 2 t ST / 4

ST / 4

"/ Kl5fl3 (UlO + UCM) dt T / 2

ST / 400

 K15K2K10 I cOSWt 2 Mm T / 2m 1

 sin (m a) t - $ n) + U: M dt.

During the period of time 5T / 4, a logical signal O acts on the direct output of the T-flip-flop 17, and a logical signal 1 on the inverse. The pulses from the output of the voltage-frequency converter 15 are fed through the logic element I 26 to the subtracting input of the reversible counter 30. the period of the reverse counting of the ST / 4 t 5T / 4 counter contents will change by

N30 -2U15

ST / 4 t 5T / 4

5T / 4

- / Ki5fi3 (Uio + uCM) dt

ST / 4

5T / 4

00

  / K2Ki0COSG t X Mm

 ST / 4m 1

 Sin (m 0) t - $ n) + C; m dt.

During the time interval 5Т / 4 on the direct output of the T-flip-flop 17, the signal of logical 1 acts, and on the inverse of logical O. As a result, the pulses from the output of the voltage-frequency converter 15 are transmitted through the logic element And 25 to the input of the reversible counter 30. direct impulse counting during which its contents change by

N% IUis "

5T / 4 t ST / 2

ST / 2 "/ Kl5fl3 (UlO + UCM) dt

5T / 4

„I n

ST / 2

-Ki5 / K2K | 0cosa t%

1 5T / 4 m 1

- lMm Sin (m CO t - V- m) + UM dt.

Thus, at the time point t ЗТ / 2 in the reversible counter 30 in the binary-additional code the number

N3o N3o + Mzo + N8b

ST / 2

 - "2KloKi5 / COSfflt I t / o

T / 2

00

X Mm Sin (m W t - Ipm) dt

m 1

25

 p K2KioKi5 p IMI sin Vi IMI.

The sign of the quadrature component is also determined by the value of the most significant bit (at 1 p 0-1, at 1 0-0).

At the time of the weekend

the pulse of the write pulse generator records the contents of the reversible counter 30 into the buffer register 34. Then, the output pulse of the shaper 12 of the reset pulses reversing

the counter 30 is set to the zero state.

The information from the buffer registers 33 and 34 is output to the bus over which the code corresponding to the effective value of the quadrature component of the alternating current is transmitted, In time intervals, O t T / 2, T t T / 2, etc., e. in odd half-periods, there is information on the bus recorded in buffer register 33, and in time intervals T / 2 t t,. ST / 2 t T, i.e. in even half-periods, - information recorded in buffer register 34. As a result, the measurement of the in-phase and quadrature components

the main harmonics of the alternating current in the proposed device is carried out by digital integration of the product of the current on the reference sine wave and cosine signals for the period, and the measured values are output

devices with a sampling period equal to the period of the measured signal. Period integration is necessary to accurately measure the components of the fundamental harmonic of a non-sinusoidal current. The sampling period, equal to half the period of the measured current, fully corresponds to the algorithms of functioning of automatic systems with thyristor controllers, for example, high-speed thyristor compensating devices.

Claims (1)

The invention The measuring transducer of the components of the main harmonic of non-temporal current according to ed. Ev, No. 1485141, of which it is, so that, in order to increase the accuracy and speed with variations in the measured current, the fifth, sixth, seventh and eighth two-input logic elements of I are additionally introduced into it , the third and fourth reversible counters, the third and fourth buffer registers connected in series to the second generator of write pulses and the second generator of reset pulses, the output of which is connected to the combined inputs of the third and fourth reversible counters, first inputs, r; sixth two-input logic elements And are connected respectively to the direct and inverse outputs of the first T-flip-flop, and the second inputs are combined and connected to the output of the first voltage-frequency converter, the first inputs of the seventh and eighth two-input logical elements And are connected respectively to the direct and inverse outputs of the second T-flip-flops, and the second inputs are combined and connected to the output of the second voltage converter - a synchronous type frequency, the summing inputs of the third and fourth reversing counters are connected The subtractive inputs are connected respectively to the outputs of the sixth and eighth two-input logic elements And respectively, and the outputs are connected respectively to the information inputs of the third and fourth buffer registers, the read inputs of which are connected to the inverse outputs of the first and of the second T-flip-flop, the C-inputs are combined and connected to the output of the second shaper of the write pulses, and the outputs are combined with the corresponding outputs But the first and second buffer registers and connected to the outputs of the measuring transducer. U 7 / 3 fS B