SU1758773A1 - Device for balancing of currents of three-phase four-wire networks - Google Patents

Abstract

Purpose: the invention relates to electrical engineering and can be used for automatic balancing of currents and compensation of reactive power in a three-phase four-wire network with time-varying parameters. SUMMARY OF THE INVENTION: A current-voltage converter, a Fourier processor, three accumulating adders, a switch and an actuator of six adjustable reactive elements, a current-voltage converter, two are inserted into the device for balancing the currents of three-phase networks. a demultiplexer, six multiplexers, twelve code multipliers by a constant number and three accumulating adders. The orthogonal components of the fundamental harmonics of the phase currents are measured using the Fourier transform in discrete form, which are then digitally processed to obtain adjustable conductivities of the symmetrizer. 2 sludge. &

Description

The invention relates to electrical engineering and can be used for automatic balancing of currents and power compensation in four-wire three-phase networks with time-varying parameters.

A device for balancing three-phase networks is known, comprising six phase-sensitive rectifiers, an effective voltage value sensor, six two voltage ratio meters, three difference units, three operational blocks, six linear amplifiers, and an actuator.

The disadvantages of this device are low accuracy due to large instrumental errors in performing analog operations and methodological errors introduced by nonlinear distortions in phase currents, since the fundamental harmonic is not provided in the device’s measuring path and the speed is low due to the inertia of analog nodes.

It is also known a device for balancing three-phase network currents, comprising a rms value of a phase voltage, a phase sequence switch, a symmetrical component filler, a voltage ratio meter, an analog-to-digital converter, a calculator of the Fourier coefficients of the main harmonic, three buffer registers, three accumulating adders, an actuator organ and block

Xi

, 01

OE

Ca

control, which includes a frequency multiplier, a zero-organ, a pulse counter, a pulse shaping unit for accumulating adders, eight triggers, element 2И, element ЗИ, element 2 OR, eight delay elements, two pulse drivers and a start button. The disadvantages of this device are low accuracy and limited frequency range, due to the use of filters of symmetrical components for the separation of currents of direct and reverse sequences, as well as limited functionality, as it is applicable only to three-wire three-phase networks

The purpose of the invention is to expand the frequency range and improve the symmetry accuracy of four-wire three-phase networks.

The use of the invention provides an increase in the accuracy and speed of balancing, the expansion of the frequency range of the device and the possibility of its use in both three-wire and four-wire three-phase networks.

The essence of the invention is that it is based on the use of the Fourier transform, which is one of the types of correlation signal processing in digital form, in which the orthogonal components (or Fourier coefficients) of the amplitudes (or root-mean-square values of currents) of the main phase gok harmonics directly, by which three control signals are formed by the parameters of three elements of the symmetrizer, connected in a triangle, and three control signals by the parameters of the three elements of the symmetrizer, soy İnönü a star.

Fig. 1 shows a block diagram of a device for balancing the currents of three-phase networks; in fig. 2 is a functional diagram of its control unit.

FIG. 1 shows a power supply 1 and a three-phase load 2, in general, variable

The device for balancing the currents of three-phase networks contains a sensor 3 of a non-quadratic phase voltage value, a switch and a current-voltage converter 5, a voltage ratio measurement 6, an analog-to-digital converter (ADC) 7, Fourier processor 8, first 9 and second 10 demultiplexers, the first - the ninth multipliers 11-19 code, the first - the sixth multiplexers 20-25, the tenth 26, the eleventh 27 and twelfth 28 multipliers of the code, the first - the sixth accumulating adders 29-34, the executive body 35 and the control unit 36 ( Fig 1).

Three signal inputs of switch 4 are connected to a three-phase network, one of the phases

which is connected to the input of the sensor 3 of the root-mean-square value of the phase voltage and to the first input of the control unit 36. The output of the sensor of the mean square value of the phase voltage is connected to the first input of the voltage ratio meter 6, and the output of the switch 4 through the current-voltage converter 5 to the second inputs of the control unit 36 and the meter 6 voltage ratio, the output of which is connected to the signal voltage the input of the ADC 7 connected by its output to the information input of the Fourier processor 8, the first and second outputs of which are connected to the information inputs of the demultiplexers 9 and 10. The control inputs of the ADC 7 and the Fourier processor 8 are interconnected and at a first output connected to the control unit 36, and combined with each other

5 control inputs of the switch 4 and demultiplexers 9 and 10 to the second output of the control unit 36. The demultiplexer 9 is the first output connected to the first information inputs of the multiplexers 21

0 and 22 and through a multiplier 11 codes to the first information inputs of multiplexers 24 and 25, the second output to the third information inputs of multiplexers 20 and

22i through a multiplier 12 code to the third 5 information inputs of multiplexers

23 and 25, and the third output - to the fifth information / isolation inputs of multiplexers 20 and

21 and through a multiplier 13 code to the fifth information inputs of multiplexers 23

0 and 24. The first output of the demultiplexer 10 is connected via a multiplier 14 of the code to the second information input of the multiplexer 23 and through a multiplier 15 of the code to the second information inputs of the multiplexers 24 and 25, the second output through the multiplier of the code 1 to the fourth information input of the multiplexer 24 and through multiplier 17 code with the fourth information inputs of multiplexers 23 and

About about. the third output through the multiplier 18 of the code - with the sixth information inputs of multiplexers 23 and 24 and through the multiplier 19 codes with the sixth information input of the multiplexer 25. Control

The 5 inputs of the multiplexers 20-25 are interconnected and connected to the third output of the control unit 36. The outputs of the multiplexers 20-22 are connected through multipliers 26-28 code to the information inputs of accumulating adders 29-31

accordingly, the outputs of multiplexers 23–25 to the information inputs of accumulating adders 32–34, respectively. The control inputs (or recording inputs) of accumulating adders 29-34 are interconnected and connected to the fourth output of control unit 36, and the outputs of accumulating adders are connected to six information inputs of the executive body 35, the control input of which is connected to the terminal control unit 36 output.

The control unit 36 includes a frequency multiplier 37, the first element 2I 38, the sample counter 39, the demultiplexer control counter 40, the null organ 41, the second element 2I 42, the first trigger 43, the second trigger 44, the third element 2I 45. the first element 2 OR 46 , the first delay element 47, the multiplexer control counter 48, the second element 2ILI 49, the third element 2ILI 50, the second delay element 51, the third trigger 52. the third delay element 53, the pulse driver 54 and the Start button 55 (Fig. 2).

The control unit 36 performs the functions of controlling (or synchronizing) the switch 4, the A / D converter 7, the Fourier processor 8. demultiplexers 9 and 10, the multiplexers 20-25, accumulating adders 29-34, and the execution unit 35.

The first and second inputs of the control unit 36 are connected respectively to the inputs of the frequency multiplier 37 and the zero-body 41, the outputs of which are connected to the first inputs of the first and second elements 2I 38 and 42. The second input of the element 2I 42 is connected to the forward output of the second trigger 44, which its single input is connected to the output of the second element 2ILI 49, connected by its first input to the reset bus and the output of the third element 2ILI 50, the first input of which is connected through the pulse shaper 54 to the Start button 55. The output of element 2 and 42 is connected to the single input of the first trigger 43, the direct output of which is connected to the zero input of the trigger 44 and the second input of the element 2 and 38 connected by its output to the first output of the control unit 36 and to the counting input of the sample counter 39, the output of which is connected to zero input of the first trigger 43, counting input of control counter 40 by demultiplexers and with the first input of the first element 2ILI 46, and through the first delay element 45 - with the second input of the first element 214LI 46 and the first input of the third element 2И 51. Code The output of the demultiplexer control counter 40 is connected to the second output of control unit 36, and the zeroing output is connected to the single input of the third trigger 52. The output of element 2IL 46 is connected to the fourth output of control unit 36 and through the second delay element 47 to the counting input of counter 48 multiplexer control, code the output of which is connected to the third output of the control unit 36. The trigger 52 is connected by its direct output to the fifth output of the control unit 36 and through the third delay element 53 with the second input of the 2ILM 50 element, and the inverse output to the second input of the 2I 51 element, the output of which is connected to the second input of the 2IL 49 element.

The principle of operation of the device is based on the initial analytical relations for the parameters of the executive body 35:, 2 2 1СоС5Ц с

, L 2 Ibs mCjg 1 I s inifc

° 3 U s W w icco5Q C | Gd gi rd L U3 U U

2 rc5; nq c J I sjnifA (

J x

Iftcosq A

U

{

T

fc J lASlmlPft

+ 3 D

IB5inC4 6

(

.Upsps e

-u-,

U3 U

where is IA, IB. c, rms phase current values;

FA, rv. pc, phase shifts of these currents with respect to the corresponding phase voltage;

U is the rms value of the phase voltage.

We introduce the notation: dx IACOS (pA: lAy lAsln Y A; BX IBCOS pb: lny - lnsin pv: IcxHccos pc: lcy lcsib pc. Where 1L.- and 1lu, QX and ley, lex and Icy are the orthogonal components of the phase currents in relation to the corresponding phase voltage.

Taking into account these designations, the expression О Мb) will be represented as

ElGa1 and ElGG U J

L1 & .IAJ- .. JL bi.Ibti-Lk.

UDft from u l U s and lv1 and

, O. Gui 1 Ic | Scr 1 b jl.

 and + u and & u S and and

Gro, 1 1du 1 Ufr. J g &

 4T and

In the proposed device, the values of IAX and 1ду, 1вх and ley. Lex and Icy are measured as the Fourier coefficients of the fundamental harmonic of the phase currents IA, IB, ic in discrete form:

(Kx S Uq SifXWtq (13)

h -

2 n Ku3 tt X coswtq, (14)

P q 1

where, b, c;

Uq lK (tq) - codes of instantaneous values of the phase currents d (t), le (t), ic (t) at the sampling points tq, called samples or samples;

Sin Urtq, COS to tq - SINHUS FUNCTION CODES

and cosine at the same sampling points tq, pre-calculated and recorded in the ROM of the Fourier processor 8;

n is the number of sampling points tq for the period of phase currents; they are counted for each phase current relative to the zero crossing of the corresponding phase voltage.

Expressions (7) - (14) form the basis for constructing a device for balancing the currents of three-phase four-wire networks.

The device works as follows.

The measurement process is carried out in three cycles: in the first cycle, Fourier coefficients (or orthogonal components) AH and the main harmonic of the phase current Id are measured, in the second cycle the Fourier coefficients IBX and ley of the main harmonic of the phase current IB, in the third cycle - the coefficients Fourier lex and Icy of the main harmonic of the phase current Ic. In all cycles the device

It works identically, so we will look at the first beat in detail.

One of the phase voltages, for example, phase A, is fed to the first input of the block.

36 control to its frequency multiplier 37 and to the sensor 3 of the rms value of the phase voltage, from the output of which the voltage is applied to the first input of the meter 6 of the voltage ratio.

The second input of the meter 6 is supplied from the converter 5 with a voltage proportional to one of the phase currents connected to the converter 5 by a switch 4, controlled by a signal from the second output of the control unit 36, depending on the cycle. At the output of the voltage meter 6, a voltage is formed that is proportional to the ratio li (t) / U, in particular, in the first clock ratio

0 lA (t) / U. The voltage from the output of the voltage ratio meter 6 is fed to the signal output of the A / D converter 7, which is in the standby mode. The voltage from converter 5 is also supplied to the second input.

5 of the control unit 36 to the null authority 41.

The balancing process starts with a start signal, which is set by the Start button 55 in the control unit 36 (Fig. 2). When this button is pressed, a pulse is formed at the output of the impulse body 54, which through the element 2ILI 50 enters the reset bus to set the device to its initial state and through element 2ILI 49 to the single input of the trigger 44.

5 The initial state of the device is as follows: the accumulating adders 20-25 are zeroed, the triggers 43, 44 and 52 in the control block 36 are set to the zero state. The low level signals from the direct outputs of the flip-flops 43 and 44, the elements 2I 38 and 42 are closed at their second inputs, and the high level signal from the inverse output of the trigger 52, the element 2I 51 is open at its second input. Baseline

5 counters 39.40 and 48 depend on how they are executed (subtracting or summing). If these counters are subtracting, then the count n is written to the subtractor 39 of samples, the count 2 is controlled by the control demux 40, and the number 6 is counted by the multiplexer control 48. If the counters 39, 40 and 48 are summed, then these numbers are written in an additional code. In both cases, each of the counters 39, 40, and 48 is zeroed out when a corresponding number of pulses arrive at it, while the zero outputs of the counters 39 and 40 form pulses, which are used as

managers. The signal from the code output of the counter 40 controls demultiplexers. supplied to the control (or address) inputs of the switch 4 and demultiplexers 9 and 10. The switch 4 is open at the first signal input and through it to the meter 6 of the voltage ratio is supplied the phase current g, and the demultiplexers 9 and 10 are open on their first exits. The signal from the code output of the counter 48 is fed to the interconnected control (or address) inputs of the multiplexers 20-25, opening them at the first input.

The trigger 44 switches to a single state and a high level signal from its direct output opens element 2I 42 for the passage of pulses from a null organ 41, which serves to highlight transitions through one of the zeros of the input signals of control unit 36, i.e. phase currents. The phase voltage from the first input of the control unit 36 is fed to a frequency multiplier 37, the multiplication factor of which is chosen equal to n, i.e. for the period of the phase current there are n periods of the output voltage of the frequency multiplier 37, which is necessary to set the n start pulses of the ADC 7 for the period of the phase current when measuring the Fourier coefficients by formulas (13) and (14).

The first output impulse of the zero-body 41, coming through the open element 2 and 42 to a single input of the trigger 43, translates it into a single state. The high level signal from the direct output of the trigger 43 is fed to the zero input of the trigger 44, sets it to the zero state and closes the element 2I 42 at its second input, and opens the element 2I 38 at the second input for passing pulses from the frequency multiplier 37. These pulses are received at the first output of the pulse unit 36 to the control input, the start input of the ADC 7, and the control input of the Fourier processor 8 to set the sin ortq and cos utq codes recorded in the processor 8 ROM. The start pulses of the ADC 7 are switched to transformations, i.e. The sampling times tq of the input voltage of the ADC 7 are proportional to the ratio iA (t) / U, and at these moments the instantaneous values of the input voltage of the ADC 7 are converted into proportional codes lAq / U (, n) that are fed to the information input of the Fourier processor 8. It forms codes of the first Aq Sin OHP ..,

NASC and NACq

I Aq COS fttq

- -r; a-at all n points of discretization

tq and their algebraic averaging is carried out, as a result we get the codes

in .gr 1Al TG

and

H

Claims (1)

1 L, | SO 5Z-C G R and proportional to the ratio of the Fourier coefficients IAX. 1d of the first harmonic of the phase current 1d (t.) To the rms value of the phase voltage U. These codes from the outputs of the Fourier processor 8 are fed to the information inputs of the demultiplexers 9 and 10, open on the first outputs. From the first output of the demultiplexer 9, the NAX code is fed through multiplexers 21 and 22, opened at the first information inputs, and then through multipliers 27 and 28 of the code to the information inputs of accumulating adders 30 and 31 and, moreover, through the multiplier 11 codes and through multipliers 24 and 25, opened through the first information inputs, to the information inputs of accumulating adders 33 and 34. From the first output of the demultiplexer 10, the Idu code enters through the multiplier 14 codes to the second information input of the multiplexer 23i through a multiplier 15 code to the second information inputs of multiplexers 24 and 25. By this point in time, i.e. after receipt of n trigger pulses to the sample counter 39, this counter is nullified and a pulse is generated at its output, which arrives at the zero input of the trigger 43, the count input of the demultiplexer control counter 40, the first input of the 2I L 46 element and through the delay element 45 to the second input of element 2ILI 46. The flip-flop 43 returns to the initial state, closing the element 2И 38 on the second input, in the counter 40 the code is changed by one and thereby switching the switch 4 and demultiplexers 9 and 10 to the second state. Through the switch 4, through its second signal input n to the converter 5 input, the phase current 1VM is applied, and the signal run of the ADC 7 is supplied from the output of voltage 6, proportional to the ratio 1V (0/1). Demultiplexer 9 pn open on their second outputs. Element 2ILI 46 and delay elements 45 and 47 sequentially write NAX, NAy codes (and then NBX and Nsy, NCX and Ncy codes) to certain accumulating adders. Thus, the output pulse of the sample counter 39, which directly arrives at the first input of element 2ILY 46, is fed through the fourth output of control unit 36 to the control inputs (recording inputs) of all accumulating adders 29-34, however, recording is made only to accumulating adders 29, 30 , 33 and 34, on the information inputs of which there is code information from the outputs of multiplexers 21,22, 24 and 25, respectively, and the recording is carried out taking into account the sign of this term proportional to the NAX IAX / U, taking into account multiplication factors (or scale factors) in expressions (8), (9), (11) and (12). With some delay, determined by the time code was written into accumulating adders 29-34 and specified by the element 47 delay, the output signal of the element 2IL And 46 is applied to the counting input of the counter 48 by controlling the multiplexers, changing its output code by one and thereby switching all the multiplexers 20-25 to the second state, in which they are open at the second input, and hence the codes available at the second information inputs of the multiplexers 23-25. arrive at the information inputs accumulating adders 32-34. With some delay, specified by delay element 45 (the delay time of this element is slightly longer than the delay time of element 47), a signal is sent from its output through element 2ILI 46 through the fourth output of control unit 36 to the control inputs of all accumulating adders and through element 47 of delay input counter 48 control multiplexers. In the accumulating adders 32-34, from the outputs of the demultiplexers 23-25, codes proportional to N & y lAy / U are recorded, taking into account multiplication factors (or scaling factors) in accordance with expressions (10) - {12), the output code of the counter 48 multiplexers 20-25 are set to the third state, in which they are opened through their third information inputs. This completes the first cycle of operation, and the device automatically proceeds to the second cycle of operation — the measurement of the Fourier coefficients of the main harmonic of the phase current i (t). For this, the signal from the output of the delay element 45 is supplied through the element 2I 51 and element 2IL14 49 on the single input of the trigger 44, switching it to one state. In the future, the operation of the device is completely repeated and in accordance with expressions (7), (9). (10) and (12) in accumulative adders 29,31,32 and 34 (in the third state of multiplexers) codes proportional to the value of IBX / U will be written, and in accordance with expressions (10) 0 (12) in accumulative adders 32 -34 (in the fourth multiplexer state), codes proportional to the iBy / U value will be recorded with the corresponding multiplication factors (or scaling factors) and signs Similarly, the device operates in the third cycle, when the Fourier coefficients of the main harmonic of the phase current lc (t) are measured. In this cycle, the control signal from the second output of the control unit 36 switches 4 to the third input and to the signal input of the ADC 7 receives the signal ic (l) / U, demultiplexers 9 and 10 open to the third output, and multiplexers 20-25 5 to In that information entry. At the end of the third cycle, in accordance with expressions (7), (8), (10) and (11), codes proportional to the value of Icx / will be written into accumulating adders 29, 30, 32 and 33 (in the fifth multiplexer state) U. and in accordance with expressions (10) - (12), accumulating codes 32-34 (in the sixth state of multiplexers) will be written down. Proportionate to Icy / U, s 5 with appropriate multiplication factors (or scale factors) and signs. At the end of the third cycle of the device in accumulating adders 0 29-34, codes NBC, NCA, NAB, NB, NC, respectively, are formed, which are proportional to the conductivities of the actuator symmetrizer 35 in accordance with expressions (7) - (12). 5, the multiplexing control counter 40 is zeroed out, and a signal is generated at its output, which is fed to the single input of the trigger 52, switching it to the single state. Low level signal with 0, the inverse output of this trigger is closed by the second input element 2I 51 for passing a pulse from the delay element 45 to bring the circuit into a working state. High level signal from the direct output 5 flip-flop 52 enters the control output 36 of the control unit 36 to the control input of the executive authority 35 and enters the six information inputs with the sum of tori 29-34 codes of conductance that affect the adjustable parameters symmetrizator. The same signal from the direct output of the trigger 52 is fed through the delay element 53 to the second input of the element 2ILI 50, the output signal of which resets the device to its original state, and then through the element 2ILI 49 to put the device into working condition for a new cycle balancing. In the future, the operation of the device is automatically repeated. Claims An apparatus for balancing currents of three-phase four-wire networks, comprising a rms phase voltage sensor connected to one of the phases, a voltage ratio meter, an analog-to-digital converter, a Fourier processor, three accumulating adders, a switch and an actuator out of six regulated reactive elements connected to line voltages of a three-phase network, and the output of the rms value of the phase voltage of the sensor is connected to the first input The voltage ratio meter connected by the output to the signal input of the analog-digital converter, the output of which is connected to the information input of the Fourier processor, the control inputs of the analog-digital converter and the Fourier processor are connected to the first output of the control unit, the outputs of the first three accumulating adders are connected with three information inputs of the executive body, and their control inputs are combined and connected to the fourth output of the control unit, the fifth output of which is connected to the control m input of the actuator, characterized in that, in order to expand the frequency range and improve the symmetry of the three-phase four-wire networks, a current-voltage converter, two demultiplexers, six multiplexers, twelve code multipliers, the fourth and sixth accumulators, one of the phases of the network is connected to the first input of the control unit, the switch is connected to the three-phase current circuit by three signal inputs, and the output through the current-voltage converter to the second input A control unit and voltage ratio meter, two outputs of the Fourier processor are connected to the information inputs of the first and second demultiplexers, the control inputs of which and the switch are combined and connected to the second output of the control unit, the first demultiplexer is connected the first output with the first information inputs of the second and third multiplexers and through the first code multiplier with the first information inputs of the fifth and sixth multiplexers, the second output with the third information inputs of the first and third multiplexers and through the second multiplication code with the third information of the fourth and Sixth multiplexers , and the third output - with the fifth information inputs of the first and second multiplexers and through the third code multiplier - with the fifth information inputs four the second and the second multiplexers, the second demultiplexer is connected by the first output through the fourth multiplier of the code to the second information input of the fourth multiplexer and through the fifth multiplier of the code to the second information inputs of the fifth and sixth multiplexers, the second output through the sixth multiplier of the code to the fourth information input of the fifth multiplexer and the seventh code multiplier to the fourth information inputs of the fourth and sixth multiplexers, and the third output through the eighth multiplier to six information The fourth and fifth multiplexer inputs and through the ninth code multiplier to the sixth information input of the sixth multiplexer, the control inputs of all six multiplexers are combined and connected to the third output of the control unit; the outputs of the first three multiplexers through the tenth to twelfth code multipliers are connected to the information inputs the first to the third accumulating adders, respectively, the outputs of the other three multiplexers are connected to the information inputs of the fourth to the sixth accumulating summers o outputs whose outputs are connected to the fourth to sixth inputs of the executive body, and their control inputs are combined and connected to the fourth output of the control unit, the control unit consisting of a frequency multiplier, a zero-body, a sample counter, a control counter for multiplexers, a control counter for multiplexers, three triggers, three elements 2 And, three elements 2ILI, three delay elements, a pulse shaper, a start button, the first and second inputs of the control unit are connected to the inputs of the frequency multiplier and e-organ whose outputs are connected to the first inputs of the first - second elements 2I, the second input of the second element 2I is connected to the direct output / k1 of the second trigger, the output of the second 211 plug to the single input of the first trigger, the direct output of which is connected to the zero input of the second the trigger and the second input of the first element 2I connected by the output to the first output of the control unit and the input of the sample counter, the output of which is connected to a point connecting the zero input of the first trigger, the first input of the first element 2IL, the input of the first element aderzhki and the control input of the counter demultipleksoremi which code output connected to the second output of the control unit, and zeroing the output - to the single input of the third flip-flop, the output of the first delay element connected to the first input of the third element 2i and the second input of the first element 2 or, ko0 yield five The second one is connected to the fourth output of the control unit and through the second delay element to the input of the multiplexer control counter, the code output of which is connected to the third output of the control unit, the direct output of the third trigger is connected to the fifth output of the control unit and through the third delay element to the second input of the third element 2IL AND, the first input of which is connected via a pulse shaper to the Start button, the output of the third element 2IL is connected to the reset bus and to the first input of the second element 2IL, the second input of which is soy Inonii 2I yield the third element, and an output connected to a single input of the second flip-flop. F .- / A / Jf. / s ™ h SS Ј. . 3 Al in S r "w 2