SU1684757A1 - Logical network diagnostic device - Google Patents

Description

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The invention relates to instrumentation engineering and can be used to diagnose logical chips and digital devices based on them.

The purpose of the invention is to increase the reliability of control due to the possibility of controlling the transients of the object of control in a given time interval.

FIG. 1 is a block diagram of a device for diagnosing logic circuits; in fig. 2 is a schematic diagram of the control unit J in FIG. 3 is a block diagram of the correlator of a torus in FIG. 4 is a schematic diagram of a RAM block; FIG. 5 - timing charts of the device.

The device (Fig. 1) contains a generator of 1 test actions, a controlled circuit 2, a power supply unit 3, a generator of 4 clock pulses, a correlator 5, a block 6 for extracting and converting current pulses, a delay line (LZ) 7, analog a digital converter (ADC) 8, initial installation unit 9, control unit 10, first 11 and second 12 comparison units, first 13 and second 14 counters, first 15 and second 16 permanent memory blocks, random access unit 17, display unit 18 with associated connections.

The device according to FIG. 2 comprises the first inverter 19, the trigger 20 for setting the operating mode of the device, the first element AND 21, the second element AND 22, the first element NAND 23 D-flip-flop 24, the second element NAND. 25, the third element And 26, the trigger 27 of turning on the display unit, the buffer element 28, the fourth element And 29, the fifth element And 30, the second inverter 31 with the corresponding connections.

The device according to FIG. 3 contains K discrete delay lines (32.1, 32.2-32.К), multipliers (33.1, 33.2 ... 33.К + 1), integrators (34.1, 34.2 ... 34. К-Н), adder 35, with corresponding connections

The delay resolution L c is selected from the condition u t, where

(jFf

FT - clock frequency.

Integrators are made on an RC circuit.

the kidneys.

The device according to FIG. four

contains eight registers 36.1,

36.2 ... 36.8, element And 37, buffer element 38, with corresponding links.

The display unit 18 includes a code generator, an LED array, and matching elements, with corresponding connections.

The device works as follows.

The test signal from the output of the test stimulus generator 1 is fed to the information input of the controlled circuit 2, in the power supply circuit of which current pulses appear as a reaction to the input test signal. These pulses are extracted, amplified, transformed into voltage pulses by a block 6 for extracting and converting current pulses, and are fed to the first input of the correlator 5, the second input of which receives a test signal from the output of the generator 1 test actions. The generation of a test signal with specified characteristics is carried out using a shift register with feedback, which allows to obtain a periodic pseudo-random sequence, in which the autocorrelation function is close to the Ј-function. The correlator 5 measures the mutual correlation function; between the signals at its first and second inputs, which is the correlation portrait of the monitored circuit 2. The ADC 8 converts the signal at the output of the correlator (correlation portrait) into a digital form that is stored in block 17 RAM. In the second comparison unit, the 12 samples of the correlation portrait of the monitored scheme are compared with the samples of the reference correlation portrait, which are stored in the second permanent memory unit 16 in digital form. The second counter 14, in accordance with the clock pulses arriving at its counting input, sets the addresses at which the samples of the reference correlation portrait are stored in the second block 16 of the permanent memory. In case all the samples of the reference correlation portrait and the measured correlation portrait of the controlled circuit are match, then in block 18 of the display the figure O is lit. At this the diagnosis is over. If at least one sample of the reference correlation portrait does not coincide with the one that is rimmed, then the control unit 10 switches the clock pulses of the 4 clock pulses to the counting input of the first counter 13, which specifies the address of the reference correlation portraits of characteristic faults stored in the first block 15 constant Memory If the first comparator block 11 of the reference correlation portrait coincides with one of the characteristic malfunctions with the measured memory stored in the memory block 17, the display unit 18 lights up The code for this characteristic fault is stored in the first permanent memory unit 15 at the same address. This completes the diagnostic process.

The initial state of the control unit 10. The triggers 20 and 27 of the control unit 10 are in a single state, the trigger 24 can be in any state. The low level of the logic signal from the inverse output of the trigger 27 prohibits the passage of clock pulses from the fourth input of the block to the diagnostic device.

The operation of the control unit 10 in a dynamic mode. By pressing the Start button on the initial setup block 3, a positive polarity pulse is generated, which, arriving at the 5th input of the control unit 10, through the inverter 31, sets the triggers 20, 24 and 27 to the zero state. High levels of logical signals from inverse the outputs of the flip-flops 27 and 20 allow the passage of clock pulses from the fourth input of the control unit 10 through the element 30 to the first output of the control unit 10, and through the element 22 to the second output of the control unit 10. Each time pulse is counted The result of the correlation portrait of the monitored circuit 2 in A1SC 8 The result of comparing these samples with the reference ones in the comparator unit 12 is fed to the second input of the control unit 10 and through the AND 23 element is written to the trigger 24 by delayed clock pulses from the sixth input of the unit 10 to the clock input of the trigger 24. When hot

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P tpp; ipv; iv termination of the rotor of the chip 14, the overflow pulse from the third input of the control unit 10 through the inverter 19 will write to the register 20 the state of trnther 24. If all the samples are a drop from the ttalonnnm, then the trigger 20 and 24 will remain in the zero state, and the overflow pulse of the counter 14 through the inverter 19, the elements of the NE-25, and the element 26 will translate into one state the trigger 27, the single signal from the direct output of which through the fifth output of the control unit Yu razrav-it indication code O (logical circuit is OK), written at zero address y in the block of the fixed memory 15. The low level of the logic signal from the inverse output of the trigger 27 will prohibit the passage of the clock pulses through the AND 30 element.

If at least one count does not coincide with the reference one, the trigger 27 will remain in the zero state, the single state of the trigger 24 by the overflow pulse of the counter 14 from the 3rd input of the control unit through the inverter 19 is written to the trigger 0, the low level of the logical signal from the inverse output which will prohibit the passage of clock pulses through the element I 22, and through the third output of the control unit 10 will prohibit writing to the operating memory unit 17. A single signal from the direct output of the trigger 20 will allow the passage of clock pulses through the element 21 to the fourth output of the control unit 10, and also allow the arrival of delayed clock pulses from the sixth input of the control unit 10 through the element 29 to the trigger input 27. The process of comparing the entire correlation portrait of the diagnosed logic with the reference correlation portraits of the logic circuit will begin with various faults in it and stored in the block 15 of the permanent memory. In each measure, the correlated portrait is compared and one of these

bogey. When they coincide, the low level logic signal that has appeared at the first input of the control unit 10 through the buffer element 28 with a delayed clock pulse from the sixth input of the control unit 10 transfers the trigger 27 to a single state, the high level of the logical signal from the output of which allows the indication of the characteristic fault code The current block 15 of the permanent memory at the address given by the counter 13.

In the event that none of the reference portraits of typical faults does not coincide with the removed one, then after a complete search of the addresses, the overflow pulse of the counter 13 arriving at the seventh input of the control unit U through the element 26 will set the trigger 27 into the unit state and 18 will highlight the code stored at the last address in block 15 of the permanent memory. This indicates that a verifiable circuit has an uncommon malfunction.

The operation of the memory block. At a high level of the logic signal at the second input of the RAM 17, the clock pulses arriving at its first input record the information into the register 36.1 and rewrite the information from the register 36.1 into the register

36.2 and so on

3

The low level of the logic signal at the second input of the memory unit 17 prohibits the recording and shifting of information in the registers 36.

The operation of the display unit 18. When the logical level of the logic signal at the control input of the code converter at all its outputs, there is a low potential, while none of the elements of the LED matrix is lit. The arrival of a high level logic signal at the control input of the code converter permits the conversion of a binary code into a potential one for its indication by an LED matrix.

The test signal (Fig. 5a) comes to the second input of the correlator 5 from the generator output 1 of the setting influences, voltage pulses go to the first input of the correlator 5 (Fig.58) from the output of the current pulse conversion unit 6, as pe5

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stock controlled circuit z on the test signal on the power circuit.

The correlator 5 measures the mutual correlation function of down input signals (Fig. 5fl, B), which is a correlation portrait (Fig.) Of the monitored circuit 2. The current pulses in the supply circuit of the monitored circuit are shown in Fig. 5

The mutual correlation function фикс of fixed delay values I, 2 s, ..., K L. is obtained at the outputs of the integrators following the multipliers. At the output of the adder 35, a continuous graph of the mutual correlation function is obtained (FIG. 5).

Claims (1)

Invention Formula A device for diagnosing logic circuits, comprising a generator of test actions, terminals for connecting a test object, an analog-to-digital converter, a first counter, a first permanent memory unit, a first comparison unit, a display unit, the first output of the first counter connected to the address the input of the first block of the permanent memory, the first information output of the cat is connected to the first input of the comparison, and the second one - to the information input of the display unit, characterized in that, in order to increase the reliability of the control, a power supply unit, a clock generator, is inserted into it, a correlator, a selection and conversion unit of current pulses, a delay line, an initial setup unit, a knob / control unit, a second comparison unit, a second counter, a second permanent memory unit, a random access memory unit, the output of the power supply unit with the power supply circuit of the monitored circuit and the input of the block for the selection and conversion of current pulses, the output of which is connected to the first input of the correlator, the second input of which is connected to the output of the generator of driving effects, the output of which is connected to the information input of the controlled circuit, the output signal of the correlator is connected to the analog input - a digital converter, the information output of which is connected to the first information input of the second of the comparison unit and with the information input of the memory block whose output is connected to the second input of the first comparison unit, dm / od of which is connected to the first input of the control unit, the second input of which is connected to the output of the second comparison unit, the second input of which is connected to the information output of the second - a horny block of permanent memory, the address input of which is connected to the first output of the second counter, the second output of which is connected to the third input of the control unit, the first output of which is connected to the input of the delay line and a clock input, a generator of driving forces; the fourth input of the control unit is connected to the output of a clock pulse generator; ROI PhE -.- VI BLOCK vnp, lHrtPHHH PGHLN J to the clock input of the analog-digital converter and to the counting input Fiopn.-r -.eiiMsn, m.iX Vi of the initial block HOI utach-.vk. -RPICHG with setting inputs -: eagle of test actions,: wow and second counters and with the fifth we-block; vnpaBJieHHH, the sixth input of which is connected to the output of the delay line and to the first input of the RAM block, the third output of the control unit is connected to the second input of the RAM block, the fourth output of the control unit is connected to the counting input of the first counter, the second output of which is connected to the seventh input control unit, the fifth output of which is connected to the input of the display unit. Fig.Z but) U Ttest JUIIUUimi ... JL, one I "WHC 1" Uis Fig 5