SU1406533A1 - Device for monitoring shape of single electric signals - Google Patents

Abstract

The invention relates to the field of measurement technology. The device for recording the form of single electrical signals contains an input unit 1, a control unit 9, an analog-to-digital converter 7, a generator of 10 clock pulses, a recovery unit 8, a correction unit 6, an analog memory block 5. The control unit 9 contains triggers 12,15,19, elements OR 16,20, counters 14,18, switches 13, 17 and comparator P. The device has an increased memory utilization efficiency by saving its volume. 1 hp f-ly, 1 ill.

Description

cl

with

but

SP

00

with

The invention relates to a measuring technique and can be used to study short-term single electrical signals.

The aim of the invention is to increase the efficiency of memory utilization by saving its volume.

The drawing shows a block diagram of the proposed device. .

The device contains an analog 2-D switch input unit, an analog memory block 5, a correction block 6, an analog-digital converter 7, a recovery block 8, a control block 9, a clock pulse generator 10, the first input of the control block 9 connected to the output of the input block 1, and the second input is connected to the Ready bus. The input of the generator 10 Tactical pulses is connected to the first output of the control unit 9, and the output to the second input of the analog-digital converter 7, the first input of the first analog switch 2 is connected to the output of the input block 1, the second input is connected to the first output of the analog-digital converter 7 The third input is connected to the first output of the recovery unit 8. The first input of the second switch 3 is connected to the control signal, the second input of the v-: is connected to the second output of the analog-digital converter 7, the third input is connected to the second output of the recovery unit 8. The first input of the third switch 4 is connected to the third output of the analog-digital converter 7, the second input is connected to the third output of the recovery unit 8, and the fourth input of the first and second switches 2 and 3 is connected to the E second output of the control unit 9, the fifth input of the first, second and the third input of the third switches 2,3 and 4 is connected to the first output of the control unit 9. The sixth input of the first and second switches 2 and 3 and the fourth input of the third switch 4 is connected to the third output of the unit. The 9 control outputs of the first 2, second 3, third 4 analog switches are connected to the first, second, third input of the analog memory block 5, respectively, and the fourth input to the generator output of 10 clock pulses. The first, second, third output of block 5 i. analog memory is connected respectively to the first and second inputs of the

0

five

0

five

0

five

0

five

0

five

ka 6 correction. The first, second and third inputs of the correction unit 6 are connected to the control signal input, and the output is connected to the first input of the analog-digital converter.

The control unit 9 controls the comparator 1 1, the first trigger 12, the first switch 1 3, the first counter 14, the second trigger 15, the first element OR 16, the second switch 17, the second counter 18, the third trigger 19, the second element OR 20, and the first input is the first input of control unit 9, and the second input is connected to the synchronization level, the first input of the first element OR 16 is the second input of the control unit, the first input of the first trigger 12 is connected to the output of the first element OR 16, and the output is the second output of block 9 control and connected to the first the input of the first switch 13, the BTOpoii input is connected to the first input of the second switch 17 and is the third input of the control unit, the output of the first switch 13 is connected to the first input of the first counter 14, the second input is connected to the first input of the second element OR 20 and to the second input of the first trigger 1 2, the output of the first counter 14 is connected to the second input of the second trigger 15 and to the second input of the first element OR 16, the output of the second trigger 15 is connected to the second input of the second switch 17 and is the output of the control unit, the output volts The first switch 17 is connected to the second input of the second counter 18, the first input of which is connected to the first inputs of the first element OR 16 and the third trigger 19, the output of the second counter 18 is connected to the second input. the third trigger 19, the output of which is the third output of the control unit 9, and with the second input of the second - element OR 20, the output of which is connected to the first input of the second trigger 15.

The device works as follows.

Before starting, the first 14 and second 18 counters are reset, the first 12, second 15 and third 19 triggers are reset. The input signal is amplified in the input device and post to the first input of the analog switch.

2, to the other input of which a calibrated amplitude control signal is received,. When the input signal transforms the sync level, the compara- tor (torus 11 generates a pulse that triggers trigger 12 into one state, thereby connecting the test and control signal to the input of analog memory block 5. The signal from the first trigger 12 permits the passage of recording pulses from generator 10 clock pulses through the first switch 13 to the input of the first counter 14. The capacity of the first counter 14 is equal to the capacity of the analog memory block 5. The overflow pulse of the first counter 14 is fed to the input of the second trigger 15 and It is monitored in the unit state, and is also fed to the input of the first trigger 12 through the first element OR 16 and translates it into the zero state. This ends the process of quickly recording the instantaneous values of the signal under investigation in analog form into the analog memory of the unit 5. The output of the second trigger 15 is connected to the control inputs of the analog switches, thereby connecting the outputs of the analog-digital converter 7 to the corresponding inputs of the analog memory block 5. Simultaneously, the signal from the second flip-flop 15 is fed to the 10-clock pulse generator, which begins to generate the frcuMTC of this moment in time, begins the process of slow reading from analog memory block 5, correcting in correction block 6, converting to ADC code 7 and writing to that same analog memory.

Simultaneously with the start of reading the information, the signal from the second trigger 15 permits the passage of read pulses through the second switch 17 to the input of the second counter 18. The capacity of the second counter 18 is equal to the capacity of the analog memory. ,

The overflow pulse of the second counter 18 is fed to the input of the third trigger 19 and sets it to one state, and also to the input of the second trigger 1.5 through the second element OR 20 and converts it to the zero state. The output of the third trigger 19 is connected to the control inputs of the first 2, second 3, and third 4 analog switches than

0

5 0 5 ЗО

Q

five .

50

five

information is provided. from the output of the analog memory block 5 through the recovery block 8, which performs the function of restoring logic levels for writing back to the analog memory of block 5.

Thus, the information read from the analog memory block 5 is closed in a ring, ensuring the circulation of the code, the recorded signal and its cyclic output.

Formula of Invention

Claims (2)

1. A device for recording the form of single electrical signals containing an input unit, a control unit, an analog-to-digital converter, a clock generator, whose input is connected to the first output of the control unit, and an output to a second input of the analog-to-digital converter, that, in order to increase efficiency, it contains three analog switches, a power-up unit, a correction unit, and an analog memory block, with the first input of the first analog switch connected to the output of the the second input is connected to the first output of the analog-digital converter, and the fourth, fifth and sixth inputs are connected to the second, first and third outputs of the control unit, respectively, the first input of the second analog switch is connected to the control signal thickness, the second input is connected to the second output analogue-digital converter, and the fourth, fifth and sixth inputs are connected to the second, first and third outputs of the control unit, respectively, the first input of the third analog switch is connected to the third output m of the analog-digital converter, and the third and fourth inputs are connected to the first and third outputs of the control unit, respectively, the outputs of the analog switches are connected to the corresponding inputs of the analog memory block, the inputs of the recovery unit are connected to the corresponding outputs of the analog memory block, and the outputs are connected respectively to the third inputs of the first and second analog switches and to the second input of the third analog switch are the outputs of the device, the first input of the correction unit is a control signal bus, a second input correction unit coupled to the first output analog memory unit, a third input coupled to a second output of the analog memory, and the output is the first input of the analog-digital converter. 2. The device according to claim 1, wherein the control unit comprises three flip-flops, two OR elements, two counters, two switches, a comparator, the first input of which is connected to the synchronization bus, and the second input is the first input of the control unit , the first input of the first element OR is the second input of the control unit, the first input of the first trigger is connected to the output of the first OR element, and the output is the second output of the control unit, the first input of the first switch is connected to 5 5 0 the first trigger, the second input is connected to the first input of the second switch and is the third input of the control unit, and the output is connected to the first input of the first counter, the second input of which is connected to the first input of the second OR element and the second input of the first trigger, the output of the first counter to the second input of the second trigger and to the second input of the first element OR, and the output of the second trigger is connected to the second input of the second switch and is the first input of the control unit; the output of the second switch is connected to the second input The second counter, the first input of which is connected to the first inputs of the second counter and the third trigger, and the output of the second counter is connected to the second input of the third trigger, the output of which is the third output of the control unit, and the second input of the second OR element, the output of which is connected to the first the entrance of the second trigger.