SU1183910A1 - Digital peak detector - Google Patents

Description

The invention relates to a pulse technique and can be used in automatic control systems and measuring devices.

The purpose of the invention is to increase the reliability of the detector due to the parallel transformation of information.

The drawing shows a functional diagram of the device.

The digital peak detector contains an analog-to-digital converter (ADC) 1, a 2 clock pulse generator, an AND 3 element, an inverter 4, a memory register 5, an adder 6, an input bus 7 with which the information input of the ADC 1 _g is connected the output of which is connected to the information input of the memory register 5 and through the inverter 4 to the first input of the adder 6, the second input of which is connected to the output of the memory register 5, and the output of the adder 6 is connected to the first input of the And 3 element, the second input of which is connected to the output of the generator 2 clock pulses and 25 clock input Hovhan ADC 1.

The digital peak detector operates as follows.

In the initial state, the memory register 5 is set to zero by an external signal (connection is not shown in the drawing), while its first (input code A) and the second (input code B) inputs have equal codes corresponding to the zero level of the measured signal at the information input ADC 1, the output of the adder 6,

’Performing together with the inverter 4 the function of the code comparator, there is a signal of the logical unit corresponding to the condition BA, which opens the element I 3 for passing the clock pulses from the output of the generator 10

Nerator 2 clock pulses to the control input of the register 5 memory.

In addition, each clock pulse corresponds to a measurement cycle.

When a measured voltage arrives at the input bus 7, the latter, in the form of a digital code, goes to the input of memory register 5, and since the value of the previous measurement cycle (corresponding to the zero input voltage on bus 7) is stored at its output, B> A allows recording in register 5 of the memory of the next value measured: value.

If the value of the measured voltage of the next measurement cycle is greater than or equal to the previous one, then the described process repeats until the input voltage starts to decrease. At the same time, code A becomes greater than code B and at the output of adder 6, a signal appears corresponding to the logic level zero, which is fed to the input of the element AND Z. and prohibits the recording of information of the subsequent measurement cycle into memory register 5, and the digital code corresponding to the peak value of the measured voltage is stored in memory register 5 until the latter is reset or the amplitude of the measured value exceeds the value of the peak voltage value stored in memory register 5.

The output signals corresponding to the peak value of the measured value and the time of its occurrence can be output to the output buses, respectively, from the outputs of the register 5 of the memory and the adder 6.

Claims (1)

DIGITAL PEAK DETECTOR, containing a memory register, analog-to-digital converter, whose input is a device input, and the output is connected to the information input of the memory register, characterized in that, in order to increase the detector's reliability due to parallel information conversion, a clock pulse generator, element I, an inverter and an adder, whose output is connected to the first input of the element I, the second input are entered into it which is connected to the output of the clock pulse generator and the clock input of the analog-to-digital converter, and the output is connected to the control input of the memory register, whose information input through the inverter is connected to the first ode adder, a second input coupled to output of the storage register. 6 1 1183