SU1665380A1 - Device for analog data entry - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to input an analog signal into digital computers in data acquisition and processing systems. The aim of the invention is to increase the number of measured parameters of the analog signal and increase the speed of information input. The device contains a comparator, integrator, switch, analog memory, analog-to-digital converter, trigger, AND element, OR element, pulse shaper. The purpose of the invention is achieved by introducing an input signal area meter into the device, which allows its use in power control systems or the average value of a periodic signal. 3 il.

Description

fe

The invention relates to automation and computing and can be used to enter information about an arbitrary analog signal in data acquisition and processing systems.

The aim of the invention is to increase the number of measured parameters of the analog signal and increase the speed of information input.

Figure 1 shows the functional diagram of the device; 2 is a schematic diagram of an integrator; FIG. 3 is a time diagram of the operation of the device.

The device for inputting analog information (Fig. 1) contains a comparator 1, an integrator 2, a switch 3, an analog memory 4, an analog-to-digital converter 5, a trigger 6, an element OR 7, an element

8 delays, element 9, shaper 10 pulses.

The source of the analog signal for the device can be a controlled three-phase bridge circuit rectifier.

The device works as follows.

The analog signal goes to switch 3 and integrator 2. Switch 3 passes the signal from integrator 2 or directly from the analog input of the device. Memory 4 at the input of the ADC 5 acts as a latch for the analog signal. The flip-flop 6 is set by the device information and sync-input to the state corresponding to the selected channel number of the switch 3, the delay element 8 and the memory 4 are started through the OR circuit.

ABOUT

about

SL

with

00

about

When an analog signal arrives at comparator 1, the latter, when the signal passes through zero (or another specified level U0) at the time point to, sets trigger 6 to the state where switch 3 opens the channel for signal passing from the output of integrator 2. At the same time the output signal of comparator 1 through the OR circuit is fed to the control input of memory 4, fixing the level of the analog signal in it. At the first input of the element And set the level of the log. 1, thus preparing the formation of a reset pulse for integrator 2. Signal The start of the A / D converter 5 is generated at time tt (Fig. 3). The delay (ti-to) is due to the time of setting the signal on the memory 4. With the arrival of the signal on the ADC 5, the launch of the analog information is converted to digital and can be read by the computer using the data readiness signal. The Data Readiness signal through the AND 9 element starts the driver 10, the integrator 2 is zeroed and restarted, and the capacitor C starts charging. When the analog signal reaches the level Uo (time point 1h), the information processing cycle is repeated. The measurement cycle starts at the time point to (Fig. 3) when the comparator 1 is triggered and ends after a half-period T / 2 at the time point t, h. Since integrator 2 is permanently connected to the signal source, capacitor C is charged during the entire half period. At time ti (for the second half period t4), the signal is fixed in memory 4.

Thus, at this moment ti (14) at the input of the ADC there is information about the area of the previous half period. From this point until time point t2, the zone At for the ADC is dead, Capacitor C is still charging until reset t2 (integrator idle). During this interval At, a loss of information occurs

D tr + Tpr + tc6p.,

where tr is the delay in triggering the ADC relative to the moment of signal fixation (in the implemented scheme tr IO μs);

Tpr is the conversion time of the ADC from the start of the ADC to the moment of receiving the exit code by the Data readiness signal;

tc6p. - formation time of the reset pulse.

In the device for measuring the voltage of the network with an ADC, performed on an integrated chip 1108 PV1, At 20 µs, and T 6.6 ms, therefore, the proportion of information loss in the measurement cycle is

At / J 0.006 (0.6%).

The device can function in the mode of programmatic measurement of the input signal, mine square meter. This is the so-called program mode when all control signals are set by a computer. In this mode, the command source sends to trigger 6 a code corresponding to the signal tracking mode. The control input of the switch 3 receives a signal that opens a channel for passing the signal directly from the analog input. The control signal to memory 4 and the trigger signal for the ADC 5 are sent through the OR 7 element to the signal.

Data readiness the measured signal value of the analog signal goes to the data bus and the measurement cycle ends 1 In addition to the described modes, the proposed analog information input device can work together (hardware-software mode): measuring the pulse area and sampling the signal value at an arbitrary point in time software . In this mode, the computer algorithm must take into account that the moment of retrieval of information should not coincide with the interval At to eliminate unreliable information. The rest of the device works exactly as described earlier.

Claims (1)

Claims An AV device for analog information comprising a switch, comparator, analog memory, analog-to-digital converter, delay element, trigger, the first input of the switch is the input of the analog information of the device, the output of the switch is connected the analog memory information input, the output of which is connected to the analog digital input, the trigger output is connected to the control input of the switch, the output of the delay element is connected to the analog digital input start ((transformer, the trigger information input is the digital information input device sync input 5, the trigger is a device synchronization input, characterized in that, in order to increase the number of measured parameters of the analog signal and increase information input speed, an integrator, a pulse shaper, an OR element, an AND element, a comparator input and an information integrator input are connected to it the first input of the switch, the comparator output is connected to the trigger setup input and the first input of the OR element, the second input of which is connected to the trigger synchronization input, the output of the OR element is connected to the input y systematic way analog memory and the input of the delay element, a first input of AND gate connected to the output flip-flop, 0 the output of the element And is connected to the input of the pulse generator, the output of which is connected to the reset input of the integrator, the output of which is connected to the second input of the switch, the ready output of the analog-digital converter is connected to the second input of the element And is the output of the device readiness, information outputs of the analog-digital converter are informational outputs of the device. Phage.1