SU1661993A1 - Synchronous binary counter - Google Patents

Abstract

The invention relates to computing, in particular to electronic computing devices. The purpose of the invention is to increase the speed - it is achieved by introducing the elements OR - NOT 12 - 14, AND - NOT 15 - 16, EXCLUSIVE OR 7 - 11 into the device containing D-flip-flops 1. 11. THIS ALLOWS TO SUPPRESS SYNCHRONES DIRECTLY BY C -D-TRIGGER INPUTS AND DO NOT COMPLETE DEVICE WHEN INCREASING THE NUMBER OF DISCHARGES. 1 IL.

Description

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The invention relates to computing, in particular, to elements of electronic computing devices, and can be used in control devices.

The aim of the invention is to increase the speed of a synchronous binary counter.

The drawing shows a schematic diagram of the device.

The device contains the first 1- sixth 6 D-triggers, the first 7 - the fifth 11 elements EXCLUSIVE OR, the first 12, the second 13 and the third 14 elements OR NOT, the first 15 and second 16 elements NAND, clock input 17, the installation input 18, direct outputs 19-24 D-flip-flops, transfer 25 output. The inverse output of the first D-flip-flop 1 is connected to the D-input of this flip-flop, and the clock input 17 is connected to the clock input of the first D-flip-flop 1, the setup input 18 is connected to the setup inputs of all D-flip-flops 1-6. The direct output of the first D-flip-flop 1 is connected to the first input of the first EXCLUSIVE OR element 7, the second input of which is connected to the direct output of the second D-flip-flop 2, and the output to the D-input of this flip-flop, the inverse output of which is connected to the first input of the first element OR-NOT 12, the second input of which is connected to the inverse output of the first D-flip-flop 1, and the output is connected to the first inputs of the second element EXCLUSIVE OR 8 and the first, the element IS-NOT 15, and the second inputs of these elements are connected to the direct output of the third D-flip-flop C, D-input of which is connected with the output of the second element EXCLUSIVE OR 8, the output of the first element AND-NO 15 is connected to the first inputs of the third element EXCLUSIVE OR 9 and the second element OR-NOT 13, the second inputs of which are connected to the inverse output of the fourth D-trigger 4, the D-input of which is connected with the output of the third element EXCLUSIVE OR 9, the output of the second element OR NOT 13 is connected to the first inputs of the fourth element EXCLUSIVE OR 10 and the second element IS-NOT 16, the second inputs of which are connected to the direct output of the fifth D-flip-flop 5, D-input which is connected to the exit even The first element EXCLUSIVE OR 10, the output of the second element AND-NO 16 is connected to the first inputs of the fifth element EXCLUSIVE OR 11 and the third element OR-NOT 14, the second inputs of which are connected to the inverse output of the sixth D-flip-flop 6, whose D-input is connected the output of the fifth element is EXCLUSIVE OR 11 direct

the outputs of the D-flip-flops and the output of the third element OR-NOT are the outputs of the device.

The device works as follows.

In the initial state, all D-flip-flops are set to the zero state by the zero level at setup input 18. After removing the zero level from setup input 18, all six D-flip-flops are in the zero state, at the D input of the first D- the trigger is set to a single signal level, at the output of the first element EXCLUSIVE OR 7 - zero signal level, zero levels at the output of the first element OR-NOT 12, at the D input of the second D-flip-flop 2, at the output of the second element EXCLUSIVE OR 8, at the output the first element AND-NOT 15 unit

0 signal level, at the first and second inputs of the third element EXCLUSIVE OR 9 unit levels, at the output of the third element EXCLUSIVE OR 9 zero signal level, at the output of the second element OR OR NOT 13 zero level, at the output of the fourth element EXCLUSIVE OR 10 zero signal level , at the output of the second element AND-NOT 16, the unit signal level, and at the output of the fifth element

0 EXCLUSIVE OR 11 zero level, at the output 25 of the transfer of the third element OR NOT 14 level zero. On the trailing edge of the first clock pulse, the first D-trigger 1 is triggered, set to

5, the second input of the EXCLUSIVE OR element 7 is the unit signal level, the unit signal level appears at the D input of the second D flip-flop 2, and the D input of the first D flip-flop 1 is set to zero. At the outputs of the remaining elements, the signal levels do not change. On the trailing edge of the second clock pulse, the first D-flip-flop 1 is set to the zero state, and the second D-flip-flop 2 goes into one state. At the output of the first element EXCLUSIVE OR 7, a single signal level remains, since at the first input of this element a single signal level is established, and

0 at the second input is set to zero, at the outputs of the remaining elements the signal levels do not change. On the trailing edge of the third clock pulse, the first D-flip-flop 1 goes into a single state 5, and the remaining D-flip-flops of their state do not change. A zero state is set at the D inputs of the first 1 and second 2 D-flip-flops, and a single state is set at the D input of the third D-flip-flop 3, since the zero state is set at the output of the first OR-NO 12 element. On the falling edge of the fourth clock pulse, the first 1 and second 2 D-flip-flops are set to the zero state, and the third D-flip-flop 3 is set to the single state, and the sixth and seventh clock pulses of the first 1 and second 2 D- the triggers change according to the binary account, and the unit state of the third D-trigger 3 will not change. On the trailing edge of the eighth clock pulse, the state of the first 1, second 2, and third 3 D-flip-flops is set to zero, and the fourth D-flip-flop 4 is set to single. On the sixteenth clock pulse, the fifth D-flip-flop 5 is set to one, and the remaining D-flip-flops to the zero state. On the trailing edge of the thirty-second clock pulse, the sixth D-flip-flop 6 is set to one, all other D-flip-flops are set to the zero state. On the trailing edge of the sixtieth third clock pulse, all D-triggers are set to one, at the output of the third element OR-NE 14 (transfer output 25) a single signal level is set. On the trailing edge of the sixty fourth quarter clock pulse, all D-flip-flops are set to the zero state, and at the output 25 of the transfer, also the zero level. The cycle is repeated. The counter allows increasing any number of bits without increasing the number of tracks, i.e. connections between elements, and, if the number of bits in the counter is odd, a AND-NOT logic circuit is established at the output of the transfer. The Formula of the Invention A synchronous binary counter containing the first — sixth D-flip-flops. clock and setup inputs, the inverse output of the first D-flip-flop is connected to the D-input of this flip-flop, and the clock input is connected to the clock input of the first D-flip-flop,

The setup input is connected to the setup inputs of all D-flip-flops, characterized in that. in order to increase speed, the first fifth elements EXCLUSIVE OR are entered into it, the first and second elements NAND, the first - the third elements OR-NOT, the direct output of the first D-flip-flop is connected to the second input of the first element EXCLUSIVE

OR, the first input of which is connected to the direct output of the second D flip-flop, and the output is connected to the D-input of the second D-flip-flop. the inverse output of which is connected to the first input of the first OR-NOT element, the second input of which is connected to the inverse output of the first D-flip-flop, and the output is connected to the second inputs of the second element EXCLUSIVE OR and the first element NAND, and the first inputs of these elements

connected to the direct output of the third D-flip-flop, the D-input of which is connected to the output of the second element EXCLUSIVE OR, the output of the first AND-NOT element is connected to the second inputs of the third element

EXCLUSIVE OR or the second element OR-NOT, the first inputs of which are connected to the inverse output of the fourth D-flip-flop, the D-input of which is connected to the output of the third element EXCLUSIVE OR, the output

the second element OR is NOT connected to the second inputs of the fourth element SPARING AND OR the second element NAND, the first inputs of which are connected to the direct output of the fifth D-flip-flop, D-input

which is connected to the output of the fourth element EXCLUSIVE OR, the output of the second element AND-NOT connected to the second inputs of the fifth element EXCLUSIVE OR, and the third element OR-NOT,

the first inputs of which are connected to the inverse output of the sixth D-flip-flop, the D-input of KOTOROTO is connected to the output of the fifth element EXCLUSIVE OR, the direct outputs of the D-flip-flops and the output of the third

OR elements are NOT device outputs.

Claims (1)

Claim A synchronous binary counter containing the first to sixth D-flip-flops, clock and installation inputs, the inverse output of the first D-trigger is connected to the D-bxod of this trigger, and the clock input is connected to the clock input of the first D-trigger, the installation input is connected to the installation inputs of all D-flip-flops, characterized in that. in order to improve performance., the first fifth elements of the EXCLUSIVE OR are introduced into it, the first and second elements are NAND, the first third elements are NOR, the direct output of the first D-trigger is connected to the second input of the first element EXCLUSIVE OR, the first input of which is connected to direct output of the second D trigger, and the output with the D-input of the second D-trigger, the inverse output of which is connected to the first input of the first element OR NOT, the second input of which is connected to the inverse output of the first D-trigger, and the output is connected to the second inputs of the second element EXCL ESCENDING OR and the first INE element, and the first inputs of these elements are connected to the direct output of the third D trigger, the D-input of which is connected to the output of the second EXCLUSIVE OR element, the output of the first AND element is NOT connected to the second inputs of the third EXCLUSIVE OR element and the second OR element - NOT, the first inputs of which are connected to the inverse output of the fourth D-trigger, the D-input of which is connected to the output of the third EXCLUSIVE OR element, the output of the second element OR is NOT connected to the second inputs of the fourth EXCLUSIVE OR element and the second AND-NOT element, the first inputs of which are connected to the direct output of the fifth D-trigger, the D-input of which is connected to the output of the fourth EXCLUSIVE OR element, the output of the second AND-NOT element is connected to the second inputs of the fifth EXCLUSIVE OR element and the third OR-NOT element, the first inputs of which are connected to the inverse output of the sixth D-flip-flop, the D-input of which is connected to the output of the fifth EXCLUSIVE OR element, the direct outputs of the D-flip-flops and the output of the third OR-NOT element are device outputs.