SU1654979A1 - Number-to-time converter - Google Patents

Abstract

The invention relates to computing and can be used in devices for converting and encoding information. The aim of the invention is to expand the field of application of the converter by providing cyclic conversion of the asynchronously time-varying input code. The converter contains a pulse generator, two registers, an input code bus, a code comparison block, a D-flip-flop, a pulse counter, two AND, / 5-flip-flop elements, a write bus, four OR elements, a reset bus, and an output bus. The converter generates a pulse sequence at intervals proportional to the sequence of input codes, and the circuit provides protection against possible failures when the pulse on the write bus coincides with the pulse on the output bus by re-recording information in the register. 2 Il.

Description

The invention relates to computing and can be used in devices for converting and encoding information.

The aim of the invention is to expand the field of application of the converter by providing cyclic conversion of the asynchronously time-varying input code.

FIG. 1 shows a structural electrical converter circuit; in fig. 2 - time diagrams of his work.

The converter contains 1 pulse generator, register 2, input code bus 3, register 4, code comparison block 5, D-flip-flop 6, pulse counter 7, And 8 element, / 5-flip-flop 9, And 10 element, write bus 11 , elements OR 12-15, tire 16 reset and output bus 17.

The Converter operates as follows.

Signals on bus 16 reset registers 2 and 4, triggers 6 and 9, and pulse counter 7, while the counter 7 records the number "2, in both registers -" 1, at least one of the most significant bits in the working range. codes (for example, in the senior bit). The latter is implemented using inverse outputs of the second discharge of the counter 7 and the high bits of the registers -2 and 4.

After the reset signal is removed, the counter 7 starts counting the clock pulses.

When counter 7 is filled with a code that matches the code in register 4, a high level appears at the output of block 5, which triggers the Ј-trigger 6.

The impulse from the output of the D-flip-flop 6 enters the output bus 17, and also through the OR element 12 gives permission to write off information from register 2 to the register 4 and through the OR element 14 resets counter 7 (with the code “2” written into it), after which the counter begins to form a new time interval. The operation of the circuit is repeated with the code in register 2 until the recording signal arrives on bus 11 in an arbitrary state.

4b

WITH

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with

moment of time. In this case, information from busses 3 is written to register 2, and with the next pulse from the output of D-flip-flop 6 it is written to register 4.

The pulses at the output of block 5 and, respectively, on the output bus 17 are formed with a period defined by the code in register 4. To eliminate the possibility of a D-flip-flop b being triggered due to a transient when information in register 4 changes (through element 13 OR) permission to compare the current code of the counter 7 and the code in register 4 only in the range of operating codes, which is provided by connecting to the inputs of the element 13 OR higher bits of the operating range codes.

The scheme provides for the elimination of possible malfunctions in the converter operation when the pulse from the output bus 17 coincides with the pulse on the write bus 11 (with such a match, the not yet established distorted code from the outputs of register 2 can be written to register 4).

The coincidence of these pulses is detected by the element And 10, the output pulse of which sets the / 5-flip-flop 9 to one state. The high potential from the output of the S-flip-flop gives permission for the passage of a pulse from the output of the zth digit of the pulse counter through the AND 8 element and the OR 12 input to the register 4 write enable input, which ensures that the already correct information is repeatedly recorded from register 2 to register 4 ( the block 5 of the code comparison is closed by a signal from the output of the element OR 13). The / 5 flip-flop is zeroed by the signal from the output of the senior relative to the / th digit of the counter through the element OR 15

Thus, in the converter, it is possible to continuously convert asynchronously changing input code into time slots corresponding to the current value of the input code.

Claims (1)

Invention Formula Converter code - the time interval containing the / 5-trigger, the first and second elements And, the pulse counter, the first the register whose information inputs are the corresponding input code buses, and the write enable input is the write bus, the code comparison block, the first information inputs of which connected to the corresponding outputs of a pulse counter, a D-flip-flop, the D-input of which is connected to the output of the code comparison unit, and the C input to the output of the pulse generator, characterized in that, in order to expand the range of application of the converter by providing a cyclic conversion asynchronously changing in time of the input code, the first, second, third and fourth elements OR and the second register are entered into it, the information inputs of which are connected to the corresponding outputs of the first register, the outputs are connected to the corresponding vuyuschimi second information input code comparing unit, the reset input is combined with the input 0 reset the first register, the / -input of the D-flip-flop, the first inputs of the third and fourth elements OR is the reset bus, and the write enable input is connected to the output of the first OR element, the first input of which is combined with the second input 5 of the third OR element and the first input of the second AND element, is connected to the output of the D-flip-flop and is the output bus, and the second input of the first OR element is connected to the output of the first AND element, the first input of which is connected to the output of the youngest of the group of average pulses and the second input is connected to the output U of the 5-flip-flop, the S-input of which is connected to the output of the second element I, the second input of which is a write bus, the # input of the RS-flip-flop is connected to the output of the fourth 5 of the OR element, the second input of which is connected to the output of the oldest member of the group of middle bits of the pulse counter, the reset input of which is connected to the output of the third element OR, the counting input is connected to the output of the pulse generator, and the outputs of the group of higher bits of the pulse counter are respectively connected to the inputs the second OR element, the output of which is connected to the enable input of the comparison block of the code comparison unit. 0 1 17 / oSif U XG $ / JO tf W, tf) Fig Ko9f / t Coda mows  A