SU1615875A1 - Selector of pulse trains - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and remote control devices. The purpose of the invention is to provide the possibility of selecting a series of pulses by duration while increasing the noise immunity. The pulse train selector contains input bus 1, generator 2 gates, elements AND 4, 6-8, 21 and 22, elements OR 9, 14, 15 and 17, triggers 10, 24 and 25, counters 11, 12 and 19 pulses, clock bus 13, pulse shaper 28, output bus 30. The goal is achieved by introducing delay elements 3 and 5, generator 16, gates, elements OR 18 and 29, pulse counter 20, elements 23 and 26 and 27, and forming new Zey. The description of the invention also provides a structural electrical circuit of the counters 11 and 12 pulses. 4 il.

Description

te. 7

The image of the device is related to the pulse technique and can be used in the devices of automation and telemechanics,

The purpose of the invention is to ensure the selection of a series of pulses in duration while simultaneously preventing interference with security.

Fig, 1 shows a structural

electrical selector circuit; FIGS. 2 and 3 are timing charts which show how the selector works; in fig. 4 is a structural electrical circuit of device pulse counters; The selector contains an input bus 1, the first generator of 2 gates, first: delay element 3, first element 4, second delay element 5, second; 6 and 6, third element

And 7, the fourth element And 8, the first element OR 9, the first trigger 10, the first counter of 11 pulses, the second counter of 12 pulses, the clock line 13, the second element of IGSH 14, the third

the element OR 15, the second generator 16 gates, the fourth element OR the 17th fifth element OR 18, the third counter 19. the pulseBz the fourth counter 20 pulses, the fifth element AND 21 the sixth element And 22, the seventh element: And 23, the second trigger 24, the third Trig ger 25, the eighth element And 26 virgins; TI element AND 27, matchmaker 28 pulses, sixth element OR 29, output bus 30,

. The input bus 1 is connected to the inputs of the delay element 3 of the generator 16, the direct output of which is connected to the first input of the element 26, the output of which is connected to the S input of the trigger 25, the R input of which is connected to the R inputs of the trigger 10 and 24 and output the element OR 17 and the inverse output — with the first input of the element AND 4 and with the first inputs of the elements 6 and 7, the second inputs of which are connected respectively to the direct and inverse inputs of the trigger 10, a. also with inputs-and control, respectively, of the meters 11 and 12, third inputs with the output of delay element 3 with the second input of element AND 4 and with the primary inputs of elements And 8 and 27, and outputs with the reset inputs, respectively, of counters 11 and 12 , the counting inputs of which are connected to the clock NINA 13, the first outputs - respectively with the first and second inputs of the element OR 14,.

g

d

0

five

five

0 5 Q

five

second outputs, respectively, with the first and second inputs of an element Sh. 15, the output of which is connected to the input of generator 2, the inverse and direct outputs of which are connected to the third inputs of elements 8 and 27, respectively, the second inputs of which are connected respectively to the inverse and direct outputs trigger 24, the S input of which is connected to the output of the element And 23, the first input of which is connected to the output of the delay element 5 and the second input of the element 21 and the second input with the output of the element 22 to the second input of the element OR-9, The first entrance, which is connected to Exit item and 4j and the output - to the C-input of flip-flop 10 '

The fourth input of the AND 8 element is connected to the first inputs of the AND 21 and 22 elements, the input of the imaging unit 28 and the direct output of the trigger 25, and the output to the first input of the OR element 29, the second input of which is connected to the output of the And 27 element and the input of the counter 20, the reset input of the counter 19 and the first input of the OR 18 element, the second input of which is connected to the output of the imaging unit 29, the output to the input of the delay element 5, and the third INPUT to the output of the AND 21 element and the counting input of the counter 19, the overflow output of which connected to the reset input of counter 20 and first m input element OR 17, the second input of which is connected to the overflow output of the counter 20 and the output bus 30.,

The output of the element OR 14 is connected to the second inputs of the elements AND 22 to 26, the third input of the element AND 21 is connected to the inverse output of the generator 16,

The timing diagram (FIG. 2) shows the diagrams of the following signals: a - pulses at the output of delay element 3, b pulses at the direct output of the generator 16 gates, c - pulses at the direct output of trigger 10, d - pulses at the output of element 26 , d - pulses at the output of element 5; delay 115 e - pulses at the inverse output of the generator 2 gates;

The time diagram (Fig. 3) shows the diagrams of the following signals, and 51

pulses on the element 3 of the delay, b - pulses at the direct output of the trigger 10, c - pulses at the inverse output of the generator 16 gates, g pulses at the output of the element I 26, g - pulses at the direct output of the generator 2 gates, e - pulses at the output of the delay element 5, g - the pulses at the output of the element OR 29, 3 - the pulses at the output of the element 21 and - the pulses at the screw 30.

In the initial state, the triggers 10, 24, and 25 and the counters 11, 12, 19, and 20 are set to the logical O state (installation circuit not shown), the clock pulses are fed to the bus 13 simultaneously with the pulses being fed to the bus 1, Reversible counters 11 and 12 operate in addition mode, if the potential of logic level 1 is applied to the input of ynpas laziness, and in subtraction mode at potential of logic level O,

The input sequence and pulses are formed by a series of pulses with a known period of following T and an unknown number of pulses and a period of subsequent series, as well as a series of impulses of interference with an unknown period of following Tj. ,, where N d - the nominal number of pulses in the series. In selectable series, individual pulses or groups of m pulses can be skipped due to the influence of a number of random factors, where m is the maximum number of additional pulses missed,

The likelihood of complete coincidence of the selected series and the series of interference of the yala due to differences in the duration of the series, period and phase. Only cases of incomplete coincidence are considered.

If the impulses of a series of interference are ahead of the impulses of the selected series (Fig. 2), the selector is sequentially

It works in two modes: capture mode and selection mode. The input AND "1 pulses" start the generator 16 of strobes, which forms strobe pulses with a duration of 5 T (figure 2.6), which is determined from the expression (1) for a given instability of the period T

AT 8 T. T

(one)

756

The delay element 3 causes the pulses delayed by the DT / 2 time (FIG. 2a), which pass through the AND 4, OR 9 elements and switch the counting trigger 10 (FIG. 2B). The reversible counters 11 and 12 measure the intervals between the input meters one by one. Before the start of the measurement of each interval, the logical state of counter O is set to each odd input impulse, the counter 12 is set to every even input pulse. On the interval

T; „. counter counting / (1 -1

2p-1 tov impulses in the add mode

- T. -2.

(2)

TU.

0

five

0

five

0

five

five

where pulse period.

At the next interval T, the counter counts the K-, clock pulses in the subtraction mode. If the intervals T {, T, ,, are equal and the number of points are K-, therefore the counter to the arrival of the next impulse overflows and is set to the logical state O. If the two intervals are equal, then T is equal to Tu, is determined. The overflow pulse from the first output of one of the meters 11 or 12 (Fig. 2d) enters the generator 2 gate, generated by the interference noise, and switches to the state of logical 1 trigger 25, which indicates the capture of Owl interference and translation selector in the regon selection.

In the selection mode, the element And 4 is closed, the switching of the counting trigger 10 is produced by overflow pulses of counters 11 and 12, arriving with a period T through the element 22, which ensures that the pulses of a series of interference interfere with the strobe pulses of the generator 2. I

The pulses at the second outputs of the reversible counters 11 and 12 are formed earlier than the overflow pulses; at the first outputs of the counters, at the time of DT / 2, therefore, the strobe pulses generated by the strobe generator 2 (Fig. 2e) coincide with the strobe pulses of the generator 16 generated by interference pulses (Fig. 26). Nepsflf him the front of the pulse from a single output of the trigger 25, by the form 28, a pulse is formed, which coincides

with the input pulse, which enters the input of the delay element 5 and, later, the delay time T) to the input of the AND 23 element. Since the trigger 25 switches to the logical 1 state through the iM impulse of the disturbance series, the delayed pulse at the output of the AND 23 element does not coincides with the output pulse of element 22, therefore trigger 24 remains in the state of logic 0, allowing the input pulses to pass through element 8 (fig 2d). The impulses of a series of interference are prohibited from strobe pulses of negative polarity, from the inverted output of generator 2, therefore at the entrance account ika 20 receives only pulses of selectable series (2g counter module 20 N Qvybiraets nym equal to the nominal number of pulses being selected series of 2nd bed

If the number of pulses in a series is greater than or equal to N (,, counter 20 generates an overflow pulse, which sets the state of logic O to triggers 10, 24, and 25 and goes to bus 30 (FIG. 2i). The missed pulses of the selected series are restored by And 21 ,

To the inputs of which a series of pulses delayed by T (Fig. 2d) and a sequence of negative-polarity strobe pulses are sent from the inverted output of the generator 16. At the time of passage and flyly, the inverse output of the generator 16 forms the potential of the upper level, allowing the pulse to pass. before the pass, delayed by the T element. 5 (fig; 2z).

In the case of a group pass, the first recovered batch pulse from the output of the element And 21 is fed through the element OR 18 to the input of the delay element 5, from the output of which it again enters the input of the element 21, Thus, for the time of passing m pulses, a sequence of m pulses is generated with a period T, which ceases with the arrival of the first after a pulse skip, exposing the input element And 21 prohibiting a gate-pulse of negative polarity

Counter Module 19 is selectable

equal to (t + 1). If a pro tzeno is more than m pulses B ;, the counter 19 overflows and sets the triggers 10, 24, 25 and the counter 20 to the logical state O. If m or less pulses are missing, the counter 19 does not have time to overflow because it is reset by the first Pulse series. At the end of the series of input pulses, the counter 19 counts (m + l) and pulses from the code of the AND 21 element and the overflow pulse sets the selector elements to their initial state.

In the case when the impulse series of pulses lags behind the impulses of the selected series (Fig. 3), the selector in the measurement mode by i pulses of the selectable series () (Fig. 3a) determines the period T. The intervals are measured and compared with the help of counters 11 and 12 When two intervals are equal, one of the counters 11 or 12 generates an overflow pulse that switches the trigger 25 to the logical 1 state and switches the selector to the pulse selection mode of a series with a period T. In this case, the driver 28 generates a pulse coinciding with the i-th impulse of the selectable series, therefore, the output pulse of the delay element 5 (FIGE) coincides with the (1 + 1) pulse of the selectable series and switches trigger 24 to the logical state 1. And element 27 starts to pass the input pulses when they enter the strobe pulses positive polarity, exposed by generator 2 on overflow pulses of counters 11 and 12 (Fig. 3D), which coincide with pulses of a selectable series. The impulses of the series of interference do not get into these strobe pulses, therefore only the impulses of the matched series, which are counted by the counter 20, are passed to the output of the element OR .29 (fig.Zh). If the number of pulses in the series is greater than or equal to the module N, the counter 20 is up , impulses a pulse to bus 30 (Fig. 2i). I

The missed impulses of the series are restored with the help of the elements of SHSh 18, the delay element 5 and are counted by the counter 19 (Fig. 3),

If the series of interference pulses continues after the termination of the selected series or the series of interference impulses arrives separately (without coincidence), the selector, after resetting to its initial state by the overflow pulse, counter 20 again begins

work in the measurement mode, it determines the period Tfj and switches to the selection mode of the interference pulses. In this case, at the output of the element OR 29 there are no pulses, since the trigger ik is in the state of logical C and the passage of pulses is prohibited by the gate-pulses of the negative polarity of the generator 2.

Thus, the proposed selector eliminates a series of interference pulses both in cases of incomplete coincidence of series, and in cases of non-coincidence.

Claims (1)

Invention Formula A series selector and fflypos, containing the first And element, the first input of which C is connected with the first inputs of the second and third And elements, the second input with the first input of the fourth And. Element, and the output with the first. the input of the first OR element, the output of which is connected to the input of the first trigger, the direct and inverse outputs of which are connected to the second inputs of the second and third elements, respectively, whose outputs are connected to the reset inputs of the first and second counters, respectively, and the pulses5 whose control inputs are connected respectively with direct and inverse outputs of the first trigger, the first outputs, respectively, with the first and second inputs of the second element OR, the second outputs, respectively, with the first and second inputs of the third element nta OR, and the counting inputs are with a clock bus, the output of the fourth element OR is connected to the R inputs of the second and third triggers, and the first input is connected to the output of the loan of the third pulse counter, whose input is connected to the output of the fifth element And, the first input which is connected to the direct output of the third trigger and to the first input of the sixth element I, the second input which is connected to the code of the second element of the RSHI, and the output to the second input of the first element OR, and the inverse output of the third trigger that and as well 0 five 0 five 0 five 0 five 0 five The first generator of gates, the input of which is connected to the output of the third element OR, pulse shaper, input and output bus, characterized in that, in order to ensure the selection of a series of pulses in duration while increasing the noise immunity, the first and second delay elements are introduced to it, the second generator gates, from the seventh to the ninth elements AND, five and sixth elements OR and a fourth pulse counter, the overflow output of which is connected to the output bus and the second input of the fourth element OR, reset input - with the overflow code of the third counter of i-pulses, and the counting input with the reset input of the third account ™ of the ticker and switch, the first input of the fifth RSHI element and the output of the sixth OR element, the first and second inputs of which are connected to the outputs of the fourth and ninth elements And, the first input of the ninth element And is connected to the first input of the fourth element And, the second inputs of the fourth and ninth elements And are connected respectively with inverse and direct outputs of the second trigger, the third inputs - respectively with inverse and n The output of the first gate generator, and the fourth input of the fourth element AND, with the output of the third trigger and the input of the pulse former, the output of which is connected to the second input of the fifth OR element, the third input of which is connected to the output of the fifth AND element, and the output through the second delay element with the first input of the seventh element And and the second input of the fifth element And, the third input of which is connected to the inverse output of the second gate generator, the input of which is connected to the input bus and through the first delay element to the second input the first element And the third inputs of the second and third elements b, and the direct output - with the first input of the eighth element And, and the output - with the input of the third trigger, and the second input of the seventh element And connected to the output of the sixth element And, and the output with S -in the second trigger of the trigger. -f I J SJ W. A A A A at f “A (O 55