SU917331A2 - Pulse duration discriminator - Google Patents

Description

(St) SELECTOR OF PULSE DURATION

one

The invention relates to a pulse technique and can be used in devices of computer technology, automation and remote control.

According to the main author. St. The no. Is known a pulse selector with a duration that contains the first pulse counter, the counting input of which is connected to the output of the first element. ta I, output with single inputs of the first and second triggers, and the setup input to zero with the zero input of the second trigger and with the output of the inverter, the second pulse counter, the counting output of which is connected to the output of the second element I, and the output with the first inputs the fourth element And, the second input of the first of which is connected to the forward output of the second trigger, the output of the third element And to the single input of the third trigger, the second input of the fourth element And connected to the input of the imaging unit and with the inverse output of the second trigger as well, and the output - with a single input of the fourth; the first trigger, the clock pulse generator, the output of which is connected to the first inputs of the first and second And elements, the second input of the first of which is connected to the input terminal and to the input of the inverter, the third input to the inverse output of the third trigger, and the second input of the second element And

10 is connected to the output of the first toiggea, and a delay element whose input is connected to the zero input of the third trigger and to the output of the phono device, and the output to the zero input of the fourth trigger 1}.

A disadvantage of the known device is low functionality, i.e. Impossibility to control impulses irrespective of the range of selection and the period of their following.

The purpose of the invention is to expand the functionality due to the control of the pulses irrespective of the range of selection and the period they follow. The goal is achieved by the fact that the device containing the first pulse counter, the counting input of which is connected to the output of the first element I, the output - to the single inputs of the first and second triggers, and the input of the set to zero - with the zero input of the second trigger and the inverter output, the second pulse counter, the counting input of which is connected to the output of the second element I, and the output to the first input of the third element I, the second input of which is connected to the single input of the third trigger, to the input of the imager to the inverse output of the second trigger, a clock pulse generator, the output of which is connected to the first inputs of the first and second elements, the second input of the first of which is connected to the input terminal and, to the input of the inverter, the third input to the output of the third trigger, and the second input of the second element. connected to the output of the first trigger, and a delay element, the input and output of which are connected respectively to the output of the imager and to the zero input of the fourth trigger, an additional pulse counter with a decoder connected to it and a multilinker are introduced neither the delay whose inputs are connected to the outputs of the decoder, and the output to the single input of the fourth trigger, the counting input of the additional pulse counter is connected to the output of the second pulse counter, the output to the single input of the third trigger, and the setup input to zero - to the installation input to zero of the second pulse counter, with zero input of the first trigger and with the output of an additional delay device, the first input of which is connected to the direct output of the third trigger, and the second input - to the synchronization input of the decoder and you Odom third element I. Via FIG. 1 shows a structural electrical circuit diagram of the device: FIG. 2 shows diagrams of its operation. The pulse selector for a long tee contains a generator of 1 clock pulses, counters 2-4 pulses J; the decoder 5, the delay line 6 multilink, triggers 7-10, elements 11-13, the inverter 14, the driver 15, the element 1b delay and the device 17 delay. Line 6 of delay contains in each link elements 18 of delay (18-1-18-p) and the element OR 19 19-1-19-P). The delay device 17 comprises a delay element 20 with an OR element 21 At the input. The counting inputs of counters 2 and 3, respectively, the elements And 11 and 12 are connected to the generator 1 clock pulses. The input to the zero of the counter 2 is connected to the zero input of the trigger 8 and through the inverter 14 to the second input of the element 11 and the input bus, and the output to the single inputs of the trigger 7 and 8. The output of the trigger 7 is connected to the other input of the element 12. The inverse output of the trigger 8 is connected to the zero input of the trigger 9, with the input of the actuator 15 and with one input of the element And 13, the other input of which is connected to the counting input of the counter 4 and the output of the counter 3 "The outputs of the bits of the counter 4 through the decoder 5 are connected to the line inputs delay, the output of which is connected n to a single input of the output trigger 10. The zero input of the trigger 10 through the delay element 1b is connected to the output of the driver 15. The installation inputs Zero of counters 3 and 4 and the trigger 7 are connected to the output of the delay device 17, the first input of which is connected to the synchronization input of the decoder 5 and to the output of the element is And 13, and the second input to the output of the trigger 9. The single input of the trigger 9 is connected to the output of the overflow of the counter 4, and the inverse output to the third input of the element And 11. The selector works as follows. In the initial state, the counters 2-4 and the triggers 7-10 are in the zero state. Elements 11 and 12 are closed at the second inputs, and element 13 at the first input are zero signals. The overflow time of counter 2 determines e1g the minimum duration of the selected pulse f (the lower threshold of selection). The total overflow time of counters 3 and 4 determines the selection range Cn the delay time of element 16 selects from paBHbiMH iji The overflow time of counter 3 tj is chosen to be less than the overflow time of counter Zu, T, e.to, t, Delay time of one link in line 6 delays are equal to the same value, with the value of tij and the number of links n chosen from the condition; (n + 1) The input pulse of positive polarity is fed to the input of the inverter T, as a result of which the setting signal of the installation input of the counter 2 is removed and from zero . the trigger input 8, and also enters the input element 11 And (time tij, Fig. 2). 11 And opening the element, the pulses from the generator and the clock tori 1 begin to arrive at the input of counter 2. If the duration of the input pulse exceeds the lower selection threshold, then counter 2 is filled with pulses before overflow. The overflow impulse of counter 2 sets triggers 7 and 8 into one state. After the overflow of the counter 2, it begins to be filled again with the clock pulses of the generator 1 (instant 1n, fig.2). When set to one state trigger & the zero signal from its inverse output closes And 13 at the second input. When the trigger 7 is set to one, the element 12 And opens at the second input and starts filling the counter with 3 clock pulses of the generator 1 before filling. Overflow pulses of counter 3 (times t, t, 1,, Fig. 2). are counted by a counter k, the reading of which varies along the trailing edge of the counting pulse. The output signals of the counter bits go to the decoder 5 but the signal on one of the outputs of the decoder 5 is generated only when a probing pulse arrives at its synchronization input from an element 13, which until the end of the monitored pulse is closed by a zero signal from the inverse output of the trigger 8.. At the end of the monitored pulse (time instant 1e, fig. 2), element 11 is closed, after which the clock pulses are stopped by counter 2, and the single signal of inverter 1 returns counter 2 and trigger 8 to its initial state. When resetting to initial condition 8, a single signal from its inverse output opens element 13 at the second input, confirms the initial state of the three | - generator 9 and enters the input of shaper 15. At the output of shaper 15 there appears a short pulse that arrives at the input of delay element 16, rem delay which. equal to the upper selection threshold ti. After the end of the input monitored pulse of a predetermined duration, the counter 3 continues to count the clock pulses until it overflows, the pulse of the overflow of counter 3 through the element 13, opened at the second input, enters the synchronization input of the decoder 5, while the corresponding output of the decoder 5 forms a pulse . It also arrives at a delay device 17, at the output of which, through a delay time which is selected from the condition of forming a pulse at the output of the decoder of a set duration, at the time t in FIG. 2, a reset pulse of counters H. and trigger 7 is generated. Since the overflow time of the counter is chosen to be less than the overflow time of the counter, the overflow pulse of counter 3 after the end of the input pulse (time t, Fig. 2) appears earlier than the pulse of triggering 7 and 8 into one state from the output of counter 2 by the next controlled pulse (time tg, fig. 2), therefore the pulse from the output of counter 3 passes through element -13 before the latter closes on the second input signal with rigger 8 when installed in a single state of the pulse counter overflow 2 the following controlled pulse, thereby providing a reset state counters 3 and 4 are always to HA. control their next input pulse, which allows control7177,318

The next input impulse of the unrolled pulse arrives at the same time as the previous memory ends without the zero input of trigger 10, i.e. Additional restrictions on the selection range and the duration of the period of input pulses. The pulse Q of the output of the decoder 5 enters the corresponding input of the delay line 6, each of whose links and delay the pulse by time C equal to the filling time of counter 3. With an arbitrary reading of the counter's head at the time of gating The decoder 5 at its synchronization input, generated at the output of the decoder 5, a pulse arrives at the (t + 1) -th link of the delay line 6, the min of the previous m links, and is delayed by the line 6 for the time (p-t) C. The impulse from the output of the delay line 6 sets the tri1- ger 10 to a single state, on the direct output of the flip-flop 10, thus the leading edge of the output pulse is formed (time t.-, Fig. 2) The total delay of the leading edge of the output pulse relative to the front the front of the controlled pulse is determined by the sum of the following delays: t is the delay by counter 2 at the time of its overflow equal to the lower threshold of selection; vj is the delay by counter 3 at the time of its overflow; the delay by the counter k at its indication equal to t, since the counter k counts the overflow pulses of the counter Zr (n-m) Jj - the delay by the delay line 6 when the pulse is applied to it, the first m links to it. The total delay of the leading edge tj ru + tfj + mqij-ln-noiuj ti) or after simplification) .1G, (3; and taking into account (1) we get 1, the leading edge of the selectable pulse is delayed by the time of the upper ThG selection threshold The falling edge of the output pulse is generated by the delayed pulse of the selected falling edge by the delay element 1b of the delayed edge of the output pulse relative to the falling edge of the monitored pulse by the same time tlj as the leading edge, therefore the output pulse of the device is equal to at When the next pulse arrives at the selector input (time tg, fig. 2), element 11 again opens and the counter begins to fill with 2 pulses from generator 1. If the duration of the input pulse exceeds the lower selection threshold, then counter 2 overflows Triggers 7 and 8 are set to one state. After trigger 7 is set to one, Element 12 is opened and filling of counters 3 and 4 with clock pulses begins. If by the time counter 4 overflows, the input pulse does not end ( the input pulse exceeds the upper selection threshold), then the overflow pulse of the counter k is fed to the single input of the trigger 9 and sets it to the single state. When this zero signal from the inverted output of the trigger 9 is fed to the inputs of the element And 11 and the imaging unit 15, closes the element. And 11 and stops further filling the counter with 2 clock pulses (time t, Fig. 2). A single signal from the direct output of the trigger 9 through the delay device 17 returns to its initial state the counters 3 and the trigger 7. In this state, the circuit remains until the end of the input pulse. After the end of the input pulse (time point, Fig. 2), the signal from the inverter 14 returns to its initial state counter 2 and triggers 8 and 9. When the selector of the third pulse arrives at the input (time t, fig. 2), element 11 again opens. , and the counter 2 begins to be filled with generator 1 pulses. If the input pulse duration is less than the lower selection threshold, then counter 2 does not overflow, because at the end of the input pulse (time-time t, fig. 2) the single signal is from inverter output 14 returns to the original state of schetik 2.

The design features of the proposed device allow the selection of duration pulses for arbitrary values of the selection range and the follow-up period of the input pulses without their limitations and independently of these values, while maintaining the duration and temporal arrangement of the input pulses.

Claims (1)

1. USSR author's certificate. № VOB + OT, cl. H 03 K 5/20, 11.03.79