SU1111253A1 - Voltage-to-frequency converter - Google Patents

Abstract

VOLTAGE CONVERTER TO FREQUENCY, containing a comparator, NAND element, integrator, the first input of which is the device input, and the output is connected to the input of a comparator, clock generator, the first trigger, the output of which is connected to the first input of the NAND element , the source of the reference current, and the switch, the output of which is connected to the second input of the integrator, characterized in that, in order to improve the accuracy, two elements AND, the second, third and fourth triggers, the delay element are introduced into it. one-shot, and a reversing switch, with the first input of the first element And connected to the output of the clock frequency generator, the output of the first element And through the first trigger connected to the first input of the second element And, the output of which through the second trigger connected to the second input of the element IS-NOT, the output of which connected to the control input of the switch, and through a delay element to the counting input of the third trigger, the output of the comparator is connected to the R inputs of the third and fourth triggers and is the output of the device, the first output The third trigger is connected to the second input of the second element I and to the control input of the reversal switch, the second output of the third trigger through the one-shot is connected to the S input of the fourth trigger, the output of which is connected to the second input of the first element I, and the source of the reference current is connected via a reversing switch to the analog input of the switch. ND SL SO

Description

The invention relates to the field of information-measuring equipment, in particular, to voltage-to-frequency converters, and can be used in control systems with analog-to-digital conversion of information. A voltage-to-frequency converter is known, comprising a integrator a comparator, two triggers, a clock generator, two logical elements of a match, two reference voltage sources AND a pv key C1. A disadvantage of such a device is the low conversion accuracy. The closest in technical essence to the present invention is a voltage-to-frequency converter containing an integrator, the output of which is connected through a comparator to the D input of a trigger, the output of which is connected to the control input of the switch and the first input of the NAND element, clock generator, output which is connected to the second input element of the NAND and the counting input of the trigger, the source of the reference current connected through a switch to the input of the integrator C2. A disadvantage of the known device is the low accuracy due to the influence of the instability of the trigger delays of the trigger and the switch on the reference time interval. The purpose of the invention is to increase accuracy. The goal is achieved by the fact that the voltage-to-frequency converter contains a comparator, an NAND element, an integrator whose first input is the device input and the output is connected to the comparator input, clock generator, the first trigger, whose output is connected to the first input element NAND, the source of the reference current and the switch, the output of which is connected to the second input of the integrator, introduced two elements AND, the second, third and fourth triggers, a delay element, one vibrator and a reversing switch The first input of the first element is connected to the output of the clock generator, the output of the first element: And through the first trigger is connected to the first input of the second element AND, the output of which through the second trigger is connected to the second input of the NAND element whose output is connected to the control the input of the switch and through the delay element to the counting input of the third trigger, the output of the com-. the paratrooper is connected to the R-inputs of the third and fourth triggers and is the device output, the first output of the third trigger is connected to the second input of the second element of Inc to the control input of the reversing switch, the second output of the third trigger is connected to the S-input of the fourth trigger, whose output connected to the second input of the first element And, and the source of the reference current through the reversing switch is connected to the analog input of the switch. FIG. 1 shows a block diagram of the device; in fig. 2 timing diagrams explaining the operation of the Device The device contains an integrator 1, the first input of which is the input of the device, and the output is connected to the input of the comparator. -2, 3 clock frequency generator, first trigger 4, the output of which is connected to the first input of the NAND element 5, the switch 6, the source 7 of the reference current, the output of the switch 6 is connected to the second input of the integrator 1, two elements 8 and 9, the second trigger 10, the delay element 11, the third trigger 12, the one-shot 13, the fourth trigger 14 and the reversing switch 15. First entry first element AND 8 is connected to the output of the clock frequency generator 3, the output of the first element I B through the first trigger 4 is connected to the first input of the second element AND 9, the output of which through the second trigger is connected to the second input of the element AND-NOT 5. The output of the element AND-NOT 5 connected to the control input of switch 6. and through the delay element 11 to the counting input of the third trigger 12, the output of the comparator 2 is connected to the R inputs of the third 12 and fourth 14 Tpjt-gers and is the output of the device. The first output of the third trigger 12 is connected to the second input of the second element I 9 and to the control input of the reversing switch 15, the second output of the third trigger 12 via the one-shot 13 is connected to the S input of the fourth trigger 14, the output of which is connected to the second input of the first element And 8. The source of the reference current 7 through the reversing switch 15 is connected to the analog input of the switch 6.

The device works as follows.

Under the influence of a constant input voltage U, the voltage at the output of integrator 1 increases linearly to the threshold of the comparator 2 (flg, 2k), which forms the output pulse (Fig. 26), confirming the initial state of the third trigger 12 and setting the fourth trigger 14 initial state (Fig. 2c). The generator 3 closes the clock frequency (Fig. 2a) fed to the input of the controlled divider formed by the first and second elements And 8 and 9, the first 4 and second 10 triggers. The fourth trigger 14, set to its initial state, allows the passage of clock pulses through the first element 8, and the outputs of the first 4 and second 10 triggers appear pulses corresponding to the divided clock frequency (Fig.). At the output of the element AND-NOT 5, by the decay of the first trigger 4, the reference time interval t begins to form (Fig. 2g). At the moment when on the outputs of the first 4 and second 10 triggers level 1 appears, the formation of the reference interval t is completed and the output of the AND-NE element 5 along the front and the slope of the first trigger 4 results in the interval pp tp (Fig. 2g) . During the reference time t, the switch 6 is open, and the current of the source of the current reference 7 is passed through the reversing switch 15 in the positive direction to the second input of the integrator 1, removing the reference charge from its capacitor. The voltage at the output of the integrator 1 decreases in proportion to the reference charge ( Fig. 2k). During the interval of the pause tn, the switch 6 is closed, and the third trigger 12 is triggered by the signal of the AND-NE element 5 delayed by the delay element 11, and the switch 7 through the switch 15 changes the polarity of the source 7 (Fig. 2h, and). At the same time, the second element And 9 prohibits the passage of pulses to the input of the second trigger 10

(Fig. 2g). Therefore, the following impulse from the output of the first trigger 4 passes through the element AND-HE 5 and forms the correction interval t k (Fig. 2g, i), during which the switchboard 6 is open and the reference current of the reverse direction passes to the second input of the integrator 1, increasing the charge its capacitor and output voltage (Fig. 2, and k). At the end of the correction interval, the switch 6 closes, the third trigger 12 triggers with a delay, and through the reversing switch 15 restores the original polarity of the connection of the reference current source 7. In this case, the single vibrator 13 forms a short impulse, resetting the fourth trigger 14,

0 which, through the first element AND 8, closes the input of the controlled divider (Fig. 2c, d). The process is repeated further.

Thus, in the proposed

5, the beginning and end of each of the time intervals (Fig. 2 and) of the flow of the reference current to the 5sods of the integrator 1 are determined by the operation of the same elements:

0 of the first element AND 8, the first trigger 4, the element IS-NOT 5 and the switch 6. If, for example, the instability of the falling edge delay leads to an increase in the reference interval tj

5 (moments t, t) in FIG. 2i), the corresponding increase in reference charge is compensated for during the correction interval t (/, since t | increases by the same time

0 as tg, but the polarity of the reference current changes in this case (moments tj tj in Fig. 2 and; dashed in Fig. 2 k). The considered component of the error does not affect the output frequency of the generator.

Based on the above, the transfer function of the converter: 1

"H -RTi (j-it;) in,

0 where R is the input resistance of the integrator 1;

1 - source current 7. The use of the invention will eliminate the effect of abate delays C1 of logic elements and a switch and increase the accuracy of the converter, especially for large conversion ratios and, accordingly, small reference time intervals.

Claims (1)

A VOLTAGE CONVERTER IN FREQUENCY, containing a comparator, an NAND element, an integrator, the first input of which is the input of the device. and the output is connected to the input of the comparator, the clock generator, the first trigger, the output of which is connected to the first input of the NAND element, the reference current source, and the switch, the output of which is connected to the second input of the integrator, characterized in that, in order to increase accuracy, two elements And, the second, third and fourth triggers, a delay element, a one-shot, and a reversing switch are introduced into it, the first input of the first element And connected to the output of the clock generator, the output of the first element And through the first trigger connected to the first input of the second AND element, the output of which through the second trigger is connected to the second input of the AND element, the output of which is connected to the control input of the switch, and through the delay element to the counting input of the third trigger, the output of the comparator is connected to the R-inputs of the third and the fourth trigger and is the output of the device, the first output of the third trigger is connected to the second input of the second element And to the control input of the reversing switch, the second output of the third trigger through a single-shot is connected to the S-input the fourth trigger, the output of which is connected to the second input of the first And element, and the reference current source is connected to the analog input of the switch through a reversing switch.