SU1241182A1 - Device for generating area centre of video pulses - Google Patents

Abstract

Fertilizer refers to a pulse technique and can be used in automatic control systems and instruments for measuring the temporal position of video pulses. The purpose of the invention is to increase the accuracy of determining the center of the video pulse area. For this, a device containing a pulse generator 5, delay elements 3 and 6, an amplitude quantizer 7, elements OR 4, 13, a group of 10 elements AND, trigger 14, counters 20, 22 pulses of the comparison unit 21, a frequency divider 17, a group 9 elements NOT, the second group of elements 11, frequency divider 15, elements 18 and 19, elements OR 16, 12. Amplitude quantizer 7 contains comparators 8. And a voltage divider implemented on resistors. The element OR 4 consists of diodes that deplete the output of the delay element 3 and the bus 2 of the video pulse. Tires, input 1 to device,: input 1 (reference voltage supply input), input 2 (video pulse voltage supply), output 23. The goal is achieved by approximating the video pulse area; trapezium square. 1 il. O) from 00 th

Description

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The invention relates to a pulse technique and can be used in automatic control systems and instruments for measuring the temporal position of video pulses.

The aim of the invention is to increase the accuracy of determining the center of the video pulse area by approximating the video pulse area by the trapezoid areas.

The drawing provides a structural diagram of the device for forming the center of the area of video pulses.

The device contains an input bus 1 (reference voltage supply input), an input bus 2 (voltage supply; video impulse), the first delay element 3, the first element of School 4, pre-. which is a diode that decouples the output of a delay element 3 and a busbar 2 video pulses, a generator of 5 pulses, a second delay element 6 (with n taps), an amplitude quantizer 7 (with n + 1 outputs) containing comparators 8 and a voltage divider , executed on resistors, group 9 elements NOT, group 10 elements AND, group 11 elements AND, element OR 12 element IL 13, trigger 14, frequency divider 15, made for example, on a trigger with a counting input, element ШШ 16, divider 17 parts , executed, for example, on a trigger with a counting input, the elements And 18, 19, the counter 20, the comparison unit 21, the pulse counter 22, the output bus 23.

Moreover, the first device input bus is connected to the first input of the amplitude quantizer 7, the second device input bus is connected to the input of the first, delay element 3, the output of which is connected to the first input of the first element OR 4, the output of which is connected to the counting input of the trigger 14, with the second the input of the amplitude quantizer 7 and with the starting of the generator of 5 pulses, the output of which is connected to the input of the second delay element 6, the outputs of the second delay element are connected to the first inputs of the first group of elements And 10, W The left inputs of which are connected to the outputs of the amplitude quantizer, and the outputs of the first group of elements AND 10 are connected to the inputs of the second element OR 13, the output of which is connected to the input of the first frequency divider 17, the zeroing inputs

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the first 20 and second 22 pulse counters are interconnected, and the bit outputs are respectively connected to the first and second inputs of the comparison unit 21, the second input of the device is connected to the second input of the first element OR 4, the inverse and direct outputs of the trigger 14 are connected to the first inputs of the first 18 and BTopOJPO 19 elements And, the outputs of which are connected to the counting inputs of the first 20 and second 22 pulse counters, respectively, the outputs of the second delay element connected to the first inputs of the second group of elements 11, the second inputs which are connected to the outputs of the amplitude quantizer, and the inputs are connected to the inputs of the third element SHSh 12, the inputs of the group of elements HE 9 are connected to the corresponding outputs of the amplitude quantizer, and the outputs of the group of elements HE 9 are connected to the third inputs of the first group of elements And 10, the outputs of the first frequency divider 17 and the third element OR 12 are connected respectively to the first and second inputs of the fourth element. OR 16, the output of which is connected to the second input of the first element AND 18 and to the input of the second frequency divider 15, the output of the comparison unit is connected to the zeroing input of the first pulse counter 20 and to the Stop input of the pulse generator 5.

The device works as follows.

In the initial state, the bus 1 is supplied with a reference voltage equal to the maximum value of the input voltage. . Trigger 14. - in the zero state, the unit level from its inverse input is present at the first input of the element And 18, and the zero level from its direct output keeps in the closed state at the first input element And 19. Nullity counters 20 and 22, 5 pulse generator stopped.

At the exits. Comparators 8 - the zero level. Elements AND groups 10 are kept in the closed state by the zero level from the same outputs of amplitude quantizer 7, and elements AND groups II are held on the second input in the closed state by n31

the left level from the output of the amplitude quantizer 7.

At the third inputs of elements AND group 10 there are single levels from the outputs of the corresponding elements NOT of group 9.

; An input signal in the form of a video pulse of arbitrary shape is fed to the bus 2, to the delay element 3 and through the OR element 4 to the counting input of the trigger 14, to the triggering input of the generator 5 pulses and to the second input of the amplitude quantizer 7.: The trigger 14 is transferred to the state one In this case, the unit level from its direct output goes to the first input of element AND 9, and the zero level from the inverse output keeps the element 18 in the closed state. At the output of the pulse generator 5, a sequence of pulses appears, and first exit amplitude quantizer 7 - a unit level, which is fed to the second input of the first element And group 10.

In the delay element 3, the video pulse is delayed by the delay time tj / j equal to the maximum possible video pulse duration at the first threshold level (known a priori) plus the delay time of the pulse from the generator output 5 pulses caused by its passage through delay element 6, elements of group 10, element OR 13, frequency divider 17, element OR 16, frequency divider 15, element AND 19, plus transient time. processes in the counter 22. A pulse from the output of the generator 5 pulses is fed to the delay element 6 with n leads, and the delay time between two adjacent taps t is chosen to be somewhat longer transients in counters 20 and 22. The pulses from the first tap of the delay element 6 pass t through the first element AND of group 10 with the pulse frequency of the generator 5 pulses per frequency divider 17 (every second pulse is passed) and through the OR element 16 to frequency divider 15 (every second pulse is passed). From the output of the frequency divider 15 through the element I 19, the received sequence of pulses goes to the counting input of the counter 20. If the voltage of the video pulse coincides with the value of Unpp 2 at the second output

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amplitude quantizer 7 appears as a single level, which is a post. It goes to the second input of the second element AND group 10, to the second input of the first element AND group 11 and to the input of the first element NOT group 9. The zero level from the output of the first element NOT group 9 through the third input spins the first element AND group 10. The pulse sequence from the first retraction of the delay element 6 passes through the first element AND group 11, through the elements OR 12, 16 to the input of the divider 15, and from its output through the element And 19 to the counting input of the counter 22. The sequence of pulses from the second retraction of the delay element 6 passes through the second element 10 nt band and the OR gate 13, the frequency divider 17, an OR gate 16, the frequency divider 15, AND gate 19 to the counting input of the counter 22.

The algorithm of the device when the voltage of a video pulse coincides with the values of the voltages of the other thresholds is similar to that described.

After the time t on the element element OR 4, the delayed video pulse, which is fed to the second input of the amplitude quantizer 7 and to the counting input of the trigger 14, transfers it to the zero state. In this case, AND 19 closes, and at the first input of AND 18, a single level appears from the inverse output of trigger 14, which ensures the passage of sequences of pulses from the output of the OR 16 element through AND 18 to the counting input of the counter 20. The operation of the other device nodes is similar described.

at the time of coincidence, the codes in the counters 20 and 22, the comparator unit 21 generates a signal that zeroes the counters 20 and 22, stops the pulse generator 5 and which is applied to the device bus 23 as a signal characterizing the center position of the video pulse. The device is in the initial state.

Claims (1)

Invention Formula A device for forming a center of video pulse area, comprising a pulse generator, a first and second delay elements, an amplitude quantizer, a first OR element, the trigger, the first and second pulse counters, the comparison unit, the first frequency divider, the second element OR, the first group of elements AND, the first input bus of the device is connected to the first input of the amplitude of the device, the second input bus of the device is connected to the input of the first delay element whose output is connected to the first input of the first element OR, the output of which is connected to the counting input of the trigger, to the second input of the amplitude quantizer and with the start of the input of the pulse generator, the transducer of which is connected to the input of the second a delay element, the outputs of the second delay element connected to pervv inputs and first group elements. And, the second inputs of which are connected to the outputs of the amplitude quantizer, and the outputs of the first group of elements AND are connected to the inputs of the second OR element, the output of which is connected to the input of the first frequency divider, the zeroing inputs of the first and second pulse counters are interconnected, and the outputs connected to the first and second inputs of the comparison unit, that is, and that, in order to improve the accuracy of determining the center of the video pulse area, the group of elements NOT is entered into it, the second group of elements I, oroy.delitel Editor M. Bandura Compiled by I.Mazurov Tehred O. Sopko Proofreader V. But ha Order 3486 / L1 Circulation 398 Subscription VNIISH USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 frequencies, first and second elements AND, third and fourth elements OR, second the device input bus is connected to the second input of the first element OR, the inverse and direct outputs of the trigger connect to the first inputs of the first and second elements respectively, the outputs of which are connected to counting ones the inputs of the first and second pulse counters, the outputs of the second delay element are connected to the first inputs of the second group of elements And, the second inputs of which are connected to the corresponding outputs of the amplitude quantizer, and the outputs are connected to the inputs of the third element OR, the inputs of the group of elements are NOT connected to the corresponding outputs of the amplitude quantizer, and the outputs of the group of elements are NOT connected to the third inputs of the first group of elements AND, the outputs of the first frequency divider and the third element OR are connected respectively Respectively with the first and second inputs of the fourth element OR, the output of which is connected to the second input of the first element AND and to the input of the second frequency divider, the output of which is connected to the second input of the second element And, the output of the comparator unit is connected to the - Auxiliary input of the lane ( - a new pulse counter and with an input. Pulse generator stop;