SU1587519A1 - Device for controlling terminal network - Google Patents

Abstract

The invention relates to automated control systems, in particular, devices for controlling the operation of a terminal network, and can be used to organize a dialogue mode of operation of a group of operators. The aim of the invention is to extend the functionality by prioritizing the input information. The device contains the first and second registers 1, 2, the first and second blocks 3, 4 memory, the first and second decoders 5, 6, elements And 7-9, 10-12, 13-15 first, second and third groups, a group of inverters 16-18, first and second elements AND 19, 20, element OR 21, trigger 22, first to fifth delay elements 23 to 27, group of elements OR 28 to 30. The goal is achieved by prioritizing the input information and issuing it immediately on the displays of jobs without loss of processing time. 2 Il.

Description

The invention relates to automated control systems, in particular, devices for controlling the operation of a terminal network, and can be used to organize a dialogue mode of operation of a group of operators.

The purpose of the invention is to enhance the functionality by prioritizing the input information.

Fig, 1 shows a block diagram of the device; in fig. 2 - codogram of the transmitted message.

The device contains the first and second registers 1 and 2, the first and second blocks 3 and 4 of the memory, the first and second registers 5 and b, the first, second, third groups of elements And 7-9, .10-12, 13-15, group inverters 16-18, the first and second elements And 19 and 20, the element ШИИ 21, the trigger 22, the first, second, third, fourth and fifth delay elements 23 - 27, the group of elements OR 28-30.

The device also contains the first group of information inputs 31, information input 32, synchronization input 33, the second group of information inputs 34-36, the group of synchronizing disturbances 37-39, the first group of information outputs of the AO, syncronization output 41 and the second group of information outputs 42 - 44 devices.

Signs of priority are entered into the codogram of the message — one bit and the character of the recipient of the codogram — four bits.

The device works as follows.

Before the operation of the device, all elements are reset. FIG. 1, the reset circuits are not shown. After switching on the device, its information inputs 31 and 32 come from a data transmission channel a sequence of codograms (Fig. 2). In this case, if the priority of the message is O, then the trigger 22 remains in the zero state, in which the element And 20 will be opened with a high potential from the inverse output.

The sync pulse arriving from the input 33, the message is entered into the register 1 from the input 31, and also the same impulse passed through the element I 20, arrives at the ele 10

15

20

15

thirty

35

40

45

50

55

There is a delay 25, where it is delayed by transient times in register 1 and then fed to the inputs of AND elements 7–9.

The decoder 5 decodes the indication of the type of message, for example, the message can be either a report, or a confirmation, or a request, etc. and opens one of the elements AND 7-9 corresponding to this type of message. Then the pulse from the output of the delay element 25 passes through the open element I 7-9 and enters the corresponding input of the memory of block 4 of the memory, which is designed as a permanent memory device, in fixed cells of which protection are the base addresses to which the incoming input should be written. - pho {) maci.

The content of the corresponding fixed memory cell is read out from block 4 to register 2, where it is recorded by a synchronization pulse from the output of the delayed-delaying element 24, the sync pulse for the time of reading the information from block 4.

The contents of register 2 as the entry address of the input information are sent to the address input of the memory unit 3, to the information input of which the information part of the corresponding message arrives. The same synchronization pulse from the output of the delay element 24, which is delayed by the element 23 at the time information is recorded in register 2, arrives at the recording input of memory block 3 and writes an input message to it.

Thereafter, the same write pulse goes through the OR element 21 to the delay element 27, where it is delayed for the time of recording the input information in the memory, and then fed to the reset input of the trigger 22, confirming its state, and resetting the register 1 to the input, setting it in the initial state.

The device with the help of the trigger 22 records the fact that the priority message arrives at the input of the device, which, without any delay in processing, should be immediately displayed on the display screen of the corresponding workplace. In the case of the arrival of a podbbnogo message, the trigger 22 is set to one state by a signal from the input 32. In this case, the element And 20 will be closed

digging low potential with inverse output,

By applying the clock to input 33, the input message is entered into register 1 from input 31, and the clock from input 33 now passes to the inputs of elements 10-12 through element 19 and element 26 of delay. At this point, the decoder 6 decrypts the address of the subscriber to whom the priority message is intended, and opens one of the elements 10-12, for example, the element 11, and the information inputs of the register 1 to the other inputs of which are connected. from the output of the delay element 26 through the elements And 11 rewrites the informative part of the input message through the elements

OR 28 to exit 42 and further - to the subscriber display screen.

Taking into account that the subscriber-recipient of the priority message at this moment could work with other information,

coming to it from the information input 35 via the synchronization signal of input 38 through AND 14 elements, the high potential from decoder 6, which opens a group of AND 11 elements, is inverted by an inverter 17, which blocks the AND 14 elements by sending a priority message during the transmission of the priority message thereby disconnecting the data transfer circuit to the display from the computer from inputs 35 and 38.

When a priority message is transmitted to the output of the device, the clock pulse from the output of the delay element 26 passes through the OR 21 element to

the input of the delay element 27, where the priority message is delayed for the time of the priority message, and then the trigger 22 and the register 1 are reset to the initial state, preparing them to receive the next message.

Claims (1)

Formula of Invention A device for controlling a terminal network containing first and second registers, first and second memory blocks, first, second and third delay elements, first decoder, AND elements of the first group, OR element and first and second And elements, information input of the first register The first information input of the device, the synchronization input of the first register is the first synchronization Q 5 0 five ABOUT 0 five 0 five 9 the first information output of the first register is connected to the information input of the first memory block, whose address input is connected to the information output of the second register, the recording control input of the first memory block is connected to the output of the first delay element, the output of the first memory block the first information output of the device, the input of the first decoder is connected to the second information output of the first register, the outputs of the first decoder are connected to the first inputs of the elements And ne your group, the outputs of which are connected to the read inputs of the second memory block, the output of which is connected to the information input of the second register, the synchronization input of which is connected to the output of the second delay element and to the input of the first delay element, the output of the third delay element connected to the second inputs of the I and Per elements - in the first group and with the input of the second delay element, the first input of the OR element is connected to the output of the first delay element, characterized in that, in order to extend the functional possibilities beyond even determine the priority of input information, entered the second decoder, the second and third groups of elements AND, the trigger, the fourth and fifth delay elements, a group of inverters and a group of elements OR, the input of the second decoder is connected to the third information output of the first register connected to the first information output of the first register, the second inputs of the elements of the second group are connected to the corresponding outputs of the second decoder, the trigger setup input is the second information the device input, the direct and inverse outputs of the trigger are connected respectively to the first inputs of the first and second elements AND. The second inputs of which are the synchronization input of the device, the input of the fourth and delay elements are connected to the output of the first And elements, the output of the fourth delay element is connected to the third and the inputs of the elements of the second group and with the second input of the OR element, the output of the second element AND is connected to the input of the third delay element, the inputs the inverter groups are connected to the corresponding outputs of the second decoder, the first and second inputs of the AND elements of the third group are respectively information and synchronization groups of device inputs, the third inputs of the AND elements of the third group are connected to the corresponding outputs of the inverter group, the first and second the inputs of the group of elements OR are connected respectively to the outputs of the elements AND of the second and third groups, the outputs of the group of elements OR are the group of information outputs of the device, the input of the fifth delay element is connected to the output of the OR element, the output of the fifth delay element is connected to the reset inputs of the trigger and the first register .