SU1575171A1 - One-digit decimal one-digit adder in code "5421" - Google Patents

Abstract

This invention relates to digital computing. The aim of the invention is to increase the speed of a decimal adder. The decimal adder contains a three-bit binary adder 1, a three-digit correcting binary adder 2, a transfer signal generating unit 21 (on NAND units 4-12,20), a correction signal generating unit 22 (on NAND elements 13-15, 19), adder 3 modulo two, the element AND-NOT 16, the elements NOT 17, 18. The decimal adder operates on the digits represented in the code "5421". 1 il.

Description

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This invention relates to gifra computing.

i The purpose of the invention is to increase the speed | of the decimal adder. The drawing shows a functional diagram of the one-decimal decimal adder in code 5421,

The one-digit decimal adder in code 5421 contains a three-bit d-binary adder 1, a three-digit correcting binary adder 2, an adder 3 modulo two, AND-NOT elements 4-16, HE elements 17 and 18, AND-NOT elements 19 and 20 The elements AND NOT 4-12, 20 form the transfer signal forming unit 21 and the K-NE elements 13-15, 19 form the correction signal generation unit 22

The adder in code 5421 works as follows

The three lower order bits of the terms (c, t b, b, CM) go to the corresponding inputs of adder 1, and the higher bits of the terms b4 and c4 go to the inputs of adder 3 modulo two. Addition of the three lower-order bits of the items follows the rules of binary arithmetic. If the output of the sum of adder 1 forms the number 5 (101 6 (110), 7 (111) or a transfer signal to the fourth bit (the number 8) occurs, then block 22 is triggered. Correction of the result also occurs when the sum of the three least significant bits equal to 4 (100) and there is an input transfer signal (e), Correction consists in adding to the value of the sum of the three lower bits of the number 3 (01). The output transfer signal (E) is formed, it is both the higher bits of the terms b and c4 equal to the logical unit j or if one of them is equal to the logical unit and the sum of the three least significant bits The terms are greater than five, or equal to four, and there is an input transfer signal (e). The corrected decimal number (b, bj, b, C) is removed from the outputs of the adder.

 L o rumula of the invention. One-digit decimal adder in code 5421, containing a three-digit binary adder, correcting a sintered binary adder, a transfer signal generating unit, a correction signal generating unit, and a modulo two, and the outputs of the three-digit ones binary adder

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connected to the first inputs of the corresponding bits of the three-digit correction binary binary adder, the outputs of the bits of which are connected to the outputs of the bits of the decimal adder from the first to the third, the output of the fourth bit of which is connected to the output of the modulo-adder two, first, second and third inputs of the block the formation of the correction signal is connected to the outputs of the first, second and third bits of the three-digit binary adder, respectively, and the output is connected to the second inputs of the first and second bits of the corrective The first trechraz is a regular binary adder, the inputs of the first, second and third bits of the first and second operands of the tenth adder are connected respectively to the first and second inputs of the corresponding bits of three bits of the second binary adder, the inputs of the fourth bits of the first and second operands of the tenth the adder is connected to the first and second inputs of the modulo two adder and to the first and second inputs of the transfer signal generating unit, the output of which is connected to the transfer output of the tenth adder, characterized in that , in order to increase speed, the decimal adder contains two NOT elements and the NAND element, the output of which is connected to the third input of the modulo two adder, and the inputs to the outputs of the first and second elements NOT, whose inputs are connected to the transfer outputs of a three-bit binary the adder and the correcting three-bit binary adder, the inputs of the third to the sixth transfer signal shaping unit are connected to the outputs of the first, second, third bits, respectively, and the transfer of the three-rectified binary adder, four the fifth input of the correction signal shaping unit is connected to the output of the first element, the transfer input of the tenth adder is connected to the seventh input of the transfer signal shaping unit, to the fifth input of the correction signal forming unit and to the transfer input of the correcting three-digit binary adder, the correction signal generating unit contains four AND-NOT elements, the inputs of the first of which are connected to the second and third inputs of the block; the inputs of the second 5157

with the first and third inputs of the block, the inputs of the third - with the third and fifth inputs of the block, the inputs of the fourth - with the outputs of the first, second and third elements of the NAND and fourth input of this block, and the output with the output of this block The transfer signal contains ten NAND elements, the inputs of the first of which are connected to the first and sixth block inputs, the second inputs to the second and sixth block inputs, the third inputs to the first and second block inputs, and even

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the second, the fourth, and the fifth inputs of the unit, the inputs of the fifth, the second, third, and fifth inputs of the unit, the inputs of the sixth, with the first, fourth, and fifth inputs of the unit, the inputs of the seventh, with the first, third, and fifth inputs blocks, inputs of the eighth with the first, fifth and seventh inputs of the block, inputs of the ninth with the second, fifth and seventh inputs of the block, inputs of the tenth with the outputs of the AND-NES elements from the first to the ninth of this block, and output with the release of this unit.

Claims (1)

Claim A single-bit decimal adder in code 5421, containing a three-bit binary adder, correcting a three-bit binary adder, block. a transfer signal generating unit, a correction signal generating unit and an adder modulo two, and the outputs of the bits of a three-bit binary adder of the bits of the correcting three-bit binary adder, the outputs of the bits of which are connected to the outputs of the digits of the decimal adder from the first to the third, the output of the fourth discharge of which is connected to the output of the adder by module two, the first, second and third inputs of the correction signal generating block are connected to the outputs of the first, second and third bits, respectively in a three-bit binary adder, and the output is connected to the second inputs of the first and second bits of the correcting three-bit binary adder, the inputs of the first, second and third bits of the first and second operands of the decimal adder are connected respectively to the first and second inputs of the corresponding bits of the three-bit binary adder, the inputs of the fourth bits of the first and second, operands of the decimal adder are connected to. the first and second inputs of the adder are modulo two. and with the first and second inputs of the transfer signal generating unit, the output of which is connected to the transfer output of the decimal adder, characterized in that, in order to improve performance, the decimal adder contains two elements NOT and an AND-NOT element the output of which is connected to the third input of the adder modulo dza, and the inputs are to the outputs of the first and second elements NOT, the inputs of which are connected to the outputs of the transfer of a three-bit binary adder and corrective three-bit binary sums ator, the inputs of the third to sixth transfer signal generation block are connected to the outputs of the first, second, and third bits and the transfer of a three-digit binary adder, the fourth input of the correction signal generation block is connected to the output of the first element NOT, the decimal adder transfer input is connected to the seventh input . a transfer signal generating unit, with a fifth input of a correction signal generating unit and with a transfer input of a correcting three-bit binary adder, while the correction signal generating unit contains four NAND elements, the inputs of the first of which are connected to the second and third inputs of the unit ^ inputs the second 1575171 with the first and third inputs of the block, the inputs of the third - with the third and fifth inputs of the block, the inputs of the fourth - with the outputs of the first, second and third elements AND NOT and the fourth input of this block, and the output - with the output of this block , the transfer signal generation block contains ten AND-NOT elements, the inputs of the first of which are connected to the first and sixth inputs of the block, the inputs of the second - with the second and sixth inputs of the block, the inputs of the third - with the first and second inputs of the block, the inputs are even— 5th - with the second, fourth and fifth inputs of the block, the inputs of the fifth with the second, third and fifth inputs 5 blocks, inputs of the sixth - with the first, fourth and fifth inputs of the block, inputs of the seventh - with the first, third and fifth inputs of the block, inputs of the eighth - with the first, fifth and seventh inputs of the block, ed inputs of the ninth - with the second, fifth and the seventh inputs of the block, the inputs of the tenth with the outputs of the AND-NOT elements from the first to the ninth of this block, and the output with the output of this block.