SU1571642A1 - Device for training control system operators - Google Patents

Abstract

The invention relates to a technique of information and computing systems and can be used in the training and training of operators in managing computing processes and complexes based on EC-based computers, as well as training dispatcher functions. The purpose of the invention is to expand the didactic capabilities of the device. The device contains a clock generator 1, a frequency divider 2, a pulse distributor 3, a program setting unit 4, an interrupt unit 9, a mode setting unit 5, a comparison unit 8, an operator panel 6 and an indicator board 7. Introduction to the device of the interrupt unit, a comparison unit the unit for setting the operation mode allows operator training to be closer to real conditions, which leads to an increase in the didactic capabilities of the device. 3 hp f-ly, 6 ill.

Description

sl j

about

1C

1

The invention relates to the technique of information and computing systems, and can be used in the training and training of operators in the management of computational processes and complexes based on EC-based computers, as well as in training dispatcher functions.

The aim of the invention is to expand the didactic abilities of the triangle.

| Figure 1 shows a block diagram of a device for training Control Planners; FIG. 2 shows a block of the block of the issuance of symbol information; FIG. 3 is a block diagram of the operator’s ggult; 4 is a block diagram of the operator's board; FIG. 3 is a block diagram of a response processing block; 6 is a block diagram of the interrupt block.

The device for training the operator of control systems (Fig. 1) contains a clock generator 1, a divider 2 frequencies, a distributor 3 pulses, a program setting unit 4, a mode setting task 5, an operator panel 6, a display board 7, block 8 comparison and block 9 interrupts.

Unit 5 assigning the operation mode (FIG. 2) contains the first decoder

10 device addresses, first counter

11 bytes of mode instructions, second decoder 12, second counter 13 of ad-permanent memory, memory 14, delay element 15, controlled clock generator 16, third counter 17 bytes of output, third decoder 18 end of data.

The operator’s console 6 (FIG. 3) is

holds the generator 19 clock pulses, the counter 20, the decoder 21, the multiplexer 22.

Indicator board 7 (figure 4) contains the registers 23 23 decoders ,, indicators 25, - 25N.

Block 8 (FIG. 5) contains the first reference response register 26, the second operator response register 27, the comparison block 28, the first error response counter 29, the first error response indicator 30, the second correct response counter 31, the second correct response indicator 32. .

Interrupt unit 9 (FIG. 6) contains a BS flip-flop 33, a delay element 34, a binary counter 35.

The operator panel 6 also contains the first and second elements HE 36, 37,

50

five

about

45

0

55

element 38, switching elements 39, 40 (buttons). The operator’s board 7 also contains an element AND 41. Block 8 also contains the first 42, the second 43 and the third 44 elements I. Block 9 contains the element И 45 "Block 5 also contains. register 46 address of the device. Block 8 contains the element And 47.

The device works as follows.

The program setting unit 4 controls the training process (training) by issuing the mode setting to unit 5.

The mode instruction contains three parts: the address of the device to which it is necessary to issue symbolic information; data address of the constant memory of symbol information; the number of bytes of character information to be returned.

In the process of writing the mode instruction, block 5, the first part — it gets into the device address register 46 (in FIG. 2), the second part — into the counter 13 of the permanent memory address, and the third part — into the counter of 17 bytes of output. The 11 bytes counter of the mode instruction and the decoder 12 are responsible for the distribution of parts of the mode instruction. When the mode instruction is written to block 5, the Ready signal is output (output 1), which indicates the start of the cycle of block 5 for issuing symbolic information to external devices.

After a time determined by the pulse edge delay element 15, a controlled oscillator of 16 clock pulses is started. For each pulse of the generator 16, a regular byte is written from memory 14, whose address is determined by counter 13, to an external device determined by the contents of register 46 and selected by the output of the decoder 10. Then the contents of counter 13 are increased by 1 and the contents of counter 17 is reduced by 1. The process of issuing symbolic information lasts until the counter is fully zeroed out 17. The zeroing factor is highlighted by the decoder 18, the signal from the output of which counter 11 is reset, as a result of which the Ready signal is set.

i

Block 5 is ready to receive the next mode instructions.

ten

15

20

25

515 16

Interrupt unit 9 provides a trigger for two mode instructions from Zlok 4 by controlling the clock pulses from amplifier 2. At the end of the set of: character information on the controller 6 of the operator, the learner presses the Enter button, thereby ensuring that the clock pulses pass through: signal input ia setup input RS-flip-flop 33 1 in the presence of a signal Ready. with a defragmer 12 block 5; comparison of the information from the reference information in block 8.

Upon receipt of the first instruction, the Ready signal decreases. and the clock pulses are prohibited during the processing of the first instruction. The symbolic information outputted from the memory block 14 of the block 5 simulates the current state of the control system and enters the indicator board 7.

At the end of the issuance of symbolic information, a Ready signal is set up, which causes the clock pulses to be resolved and the counter 35 triggers with a counting factor of 2. As a result, the second instruction reads and executes the information from the read-only memory which contains enters block 8. After the time 35 defined by delay element 34, the RS flip-flop 33 is reset, which blocks the clock pulses until the next button is pressed pki Input. At this stage, the processing of mode instructions 40 is completed and the device is ready for the next stage of the task, which begins with pressing the Enter button. When there is no key pressed on the console 6, the operator at the output of the multiplexer 22 is constantly present at a low signal level, which, through the NOT 37 element, opens the And 38 element, and the clock pulses from the generator 50 output 19 pass to the counter input 20, which performs pulse counting of pulses. When any key is pressed, the counter stops on the clock, the number of which corresponds to the number of the key pressed, since the signal from the output of the decoder through the key pressed enters the multiplexer input, and then from its output

thirty

26

the high level signal through the element 36 closes the element 38 and. The signal from the output of the mimic actuator strobe output data from the counter 20. R the case of a high level at the input of the board 7 Device selection Signal Strobe. data is fed to the input of registers 23t-23rf. The information supplied to the input of the scoreboard (from block 5) is sequentially recorded in registers 23-23N. The information from the outputs of the registers 23, -23, converted by the decoders 24j-24, is displayed by the indicators 25, -25.

The information recorded from the operator’s console 6 to the register 27 of block 8 in block 28 is compared with the reference information recorded from block 5 to the register 26. On a signal from the operator’s console, one of the counters 29 or 31 is triggered, depending on the result of the comparison: the correct answer is the counter 31, in the case of the wrong answer the counter 29.

The counting result is permanently displayed by indicators 30 and 32.

The use of the proposed device for training control system operators, created on the basis of modeling blocks, allows creating simulators with low material costs as close as possible to information models of actually operating objects both in a constructive design and in modeling the dynamics of control of computational processes and complexes. As a result, the quality of training of operators is improved, the time of their training and internship is reduced,

Claims (4)

1. Device for training control system operators containing a clock generator, a frequency divider, a pulse distributor, a training program setting unit, an operator console, a display board, a clock generator output connected to the frequency divider input, a pulse distributor outputs connected to the inputs of a training program unit group , characterized in that, in order to expand the didactic capabilities of the device, a mode setting operation unit, a comparison unit and an interrupt unit, the clock input of which This is connected to the output of the frequency divider, and the setup input is connected to the output of the operator’s console, the outputs of the group are connected to the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the outputs of the group of the operation mode setting block, and the information inputs of the indicator board The training is connected to the inputs of the group of the task setting block, the output of which is connected to the input of the interrupt block mode, the output of which is connected to the input of the pulse distributor. 2. The device according to claim 1, characterized in that the operation mode setting block comprises a register, three decoders, three counters, a block, a memory, a delay element and a controlled oscillator, the output of which is connected to the direct count input of the first counter and the entrance of the countdown the second counter, the output of which is connected to the input of the first decoder, the output of which is connected to the reset input of the third counter, the counting input of which is combined with the inputs records of the register, the first and the second (Counters whose information inputs are combined and connected to the information input of the register and together with the counting input are the inputs of a block group, the output of the third counter is connected to the input of the second decoder, the first output of which is connected to the resolution enable input, the second output connected to the enable input of the first counter, the third output connected to the enable input of the second-counter, the fourth output connected to the input of the delay element and is the output of the block, the output of the delay element ki is connected to the input of the controlled generator, the register output is connected to the input of the third decoder, the output of the first counter is connected to the address input of the block pa n 5 Q .. five The module, the output of which, as well as the outputs of the third decoder and the output of the controlled oscillator, are the outputs of the block group. 3. The device according to claim 1, characterized in that the comparison unit contains two registers, a comparison unit, two counters, three AND elements, two indicators and an NOT element whose input is connected to the output of the comparison unit whose first input is connected to the output of the first register whose recording input is connected to the output of the first element I, the first and second inputs of which, as well as the information input of the first register are the inputs of the first group of the block, the second input of the comparison unit is connected to the output of the second register, the information input and the recording input of which th, and the combined first inputs of the second and third elements And are the inputs of the second group of the block, the output of the element is NOT connected to the second input of the second element AND, the output of which is connected to the counting input of the first counter, the output of which is connected to the information input of the first indicator, the output of the comparison unit is connected to the second input of the third element AND whose output connected to the counting input of the second counter, the output of which is connected to the information input of the second indicator. 4. The device according to claim 1, wherein the interrupt unit includes an RS flip-flop, a delay element, a counter and an AND element whose output is the output of the block, the first input is connected to the RS-flip-flop output, the R-input of which connected to the output of the delay element, the input of which is connected to the output of the counter, the counting input of which is combined with the second input of the element I and is the input of the mode of the block, the installation input of which is the S input of the short-circuit, and the clock input is the third input of the element I. Јgpf SI one u a / show TO g / general “-, mdpapioe ooishe -sepoyshoy / odd . 01 7-gp® 91 I / J3v ngoujoj g / “D X9 PEGSHOS LLC HD drtHHDff :} ZWliSI FIG. 6