SU1569813A1 - Device for synchronizing channel of digit information input from magnetic carrier - Google Patents

Abstract

The invention relates to the field of computer technology, data transmission and conversion, and can be used in devices for reading and recording digital information on magnetic media. A distinctive feature of the device is that it allows to compensate for the deviation of the output frequency of the controlled oscillator, the reduction of the output frequency of the controlled oscillator itself, the absence of accumulation of error on the counter and the self-setting of the nominal (calculated) channel synchronization frequency. The aim of the invention is to expand the scope. The goal is achieved through the introduction of switch 3, triggers 7, 8, one-shot 13, clock generator 14, a HE 15 element. 2 Il.

Description

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The invention relates to computing, data transmission and conversion, and can be used in devices for reading / writing digital information on magnetic media. The purpose of the invention is to expand the scope.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagrams of the device operation.

The device contains a counter 1, a register 2, a switch 3, a digital-analog converter 4, a low-pass filter 5, a controlled oscillator 6, triggers 7 and 8, an output 9, a 10-channel input from a magnetic carrier, triggers P and 12, a single-shot 13 , the clock generator 14, the element is NOT 15, the bus 16 logical units, the bus 17 logical logical zero.

In FIG. 2, there is indicated: diagram 18 - signal at the output of the clock generator; diagram 19 is the signal at the output of the generator 6, diagram 20 is the signal at the input of the recording resolution of counter I; chart 21 - output signal 9; Figure 22 - Signal-Al at the entrance to Yu; Chart 23 is a signal at the input of recording resolution register 2 and the trigger input of the one-shot 13; chart 24 is the signal at the output of the one-shot 13; Figure 25 - signal at the input of the generator 6.

The device works as follows.

After turning on the power, before input signals from input 10 to inputs of the digital-to-analog converter 4 through the switch 3, the middle code (ftig) is fed in. From the output of the digital-to-analog converter 4 through the low-pass filter 5, the input of the generator 6 receives the average level of the analog signal (voltage) corresponding to the nominal (calculated) value of the synchronization frequency at the output of this generator 6 and equal to the frequency at output 9. Through trigger 7 and trigger 8, the operation of counter I and generator 6 is synchronized. The generator 6 and the output 9, connected to the highest bit of counter I, are equal and equalized by a positive frequency difference 19 (Fig. 2) at the output of the generator 6. The positive frequency period at the output of the controlled generator 6 through the trigger 7 and trigger 8 polo

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The differential frequency from the output of the clock generator 14 loads into the counter 1 constant Cse (taking into account the delay on the trigger 7 and 8). As a result, the period of the frequency on the output bus 9 (diagram 21) coincides with the period of the frequency at the output of the controlled oscillator 6 (diagram 19), but is opposite in phase. Deviations of the period of the frequency at the output of the generator 6 (diagram 19) from the nominal period at the output 9 (diagram 21) obtained at the highest bit of the synchronous binary counter 1, within one period not exceeding in magnitude the period of frequency 18 from the stable frequency generator 14 are compensated when synchronizing the operation of the binary counter I and generator 6.

When a signal arrives at input 10 (diagram 22), it is synchronized with the frequency from generator 14 (diagram 18) on trigger 11 and trigger 12. The synchronized input signal from trigger output 12 with its leading edge loads register 2 (diagram 23) from the output of synchronous counter 1 code corresponding to the input signal in any part of the period of the channel synchronization frequency. Simultaneously, the one-shot 13 is started, which connects (diagram 24) to the inputs of the digital-to-analog converter 4 through the switch 3 of two groups of inputs to one outputs of register 2 with a code corresponding to the moment when the input signal arrives. The greater the deviation in front of him of the front of the input signal (diagram 22) from the middle of the period of the current output frequency (diagram 21) of the channel synchronization, the greater the difference between the code written in register 2 and the average code generated in the second group of inputs of switch 3. Accordingly the greater the deviation of the analog signal (Diagram 25) from the average value of the voltage at the output of the D / A converter 4, which through the low-pass filter affects the input of the generator 6. The frequency period the output of this generator 6 (diagram 19) is respectively expanded or compressed. For the middle of the period of the output frequency (diagram 21) of the synchronization of the can g: and a positive differential is received, i.e. iootroot

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code 8-fg at the outputs of the binary counter 1. The falling edge of the input pulse on the left (low level) part of the synchronization frequency period causes a decrease (compression) of the frequency at the output of the generator 6 (diagram 19) the longer it goes (to the left of center) comes the leading edge of the input signal. Similarly, the falling front of the input signal on the positive (right) period of the channel synchronization frequency causes an increase (stretch) of the frequency period at the output of the generator 6 and a similar change in the channel synchronization frequency on the output bus 9 (diagram 21) by synchronous installation via trigger 7 and trigger 8 of counter I. After the installation time of the one-shot 13 (the signal at its output becomes low) to the inputs of the digital-to-analog converter 4 through the selector 3 of two groups of inputs to one connected to The average code that provides the nominal {estimated frequency of the channel synchronization in the absence (skip) of the input signal.

Claims (1)

Invention Formula A device for synchronizing a digital information input channel from a magnetic carrier, containing two triggers, a counter, a register, a digital-analog converter, a low-pass filter, a controlled oscillator, the synchronous input of the first trigger being an information input of the magnetic carrier channel of the device, the output of the first trigger is connected with the information input of the second trigger, the output of which is connected to the reset input on the first trigger and to the register recording enable input, the information input of the first trigger i- nen with bus logical unit mouth Q 5 0 5. 0 Q § five 13. The output of the D / A converter is connected to the input of a low-pass filter, the output of which is connected to the input of a controlled generator, the bit outputs of the first to third counter are connected to the information inputs of the register from the first to the third, the fourth bit output of the counter is connected to the fourth information input The register is the clock output of the device, characterized in that, in order to expand the field of use, two triggers are introduced into the device, a clock generator, a one-shot, jj .. m nt NOT and a switch, the first information input of the counter is connected to the information input of the fourth trigger, the first input of the first corpus of information inputs of the switch and the information input of the first trigger, the inputs of the second to fourth counter are connected to the inputs of the second to fourth first group of information inputs the switch, the second group of information inputs of which is connected to the group of outputs of the register, the group of outputs of the switch is connected to the group of inputs of the digital-analog converter, the output is The generator is connected to the input of the PE element and with the counting input of the counter, the output of the element is NOT connected to the synchronization leads of the second and third triggers, the output of the third trigger is connected to the reset input O of the fourth trigger and the write enable output of the counter, the output of the fourth trigger is connected to the information one the input of the third trigger, the output of the controlled oscillator is connected to the synchronous input of the fourth trigger, the output of the second trigger is connected to the input of the one-oscillator, the output of which is connected to the control input of the switch. 0123 56789 AB C D E F LP 19 20 1ЛШЦ1Г1Г1Ги1Г1ЛЛШШЛЛ  l I l 9 1 g jj i i  i / 2 l 22 23 24 25s V  2 j gp | 1 2 J I l I l 9  2 j gp | 1 2 J V Phage. 2