SU1330638A1 - Analog-digital device for variable scaling - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to improve the accuracy by reducing the amplitude of the pulse noise. The analog-digital device for variable scaling contains two digital-analog multipliers 1 and 2, a digital function generator 3, a group of 4 keys, a buffer register 5, a NOT element 6, an OR element 7, an AND 8 element and a synchronization unit 9. The operation of the device is based on a separate setting of the gain factors of multipliers 1 and 2. If the overall scaling factor is less than the limit value, the gain of multiplier 1 changes at a single gain value of multiplier 2. the variation of the second multiplier is multiplied, which makes it possible to reduce the amplitude of the impulse noise that occurs when the code of the scaling factor changes. 1 il. with "e (L from 00 about 9d OR 00

Description

The invention relates to automation and computing technology and can be used in analog-digital computers, automation devices and measuring equipment, the functioning algorithms of which provide for the temporary automatic adjustment of the gain factors of the scale units.

The aim of the invention is to improve the accuracy by reducing the amplitude of the pulse noise.

The drawing shows a block diagram of an analog-to-digital variable scaling device comprising first and second digital-threshold multipliers 1 and 2, digital function generator 3, key group 4, buffer register 5, NOT element 6, element OR 7, element And 8, and block 9 sync.

The device works as follows.

When the trigger pulse arrives, the output code of the buffer register 5 is set to the zero state and the output code of the digital function generator 3 to the initial position. This closes the group of 4 keys for passing the output signals of the digital generator 3 functions through them to the input of the second digital-analog multiplier 2, the output of the element NOT 6 establishes a single signal that opens the element 8 for passing the synchronization pulses through it from the second output of block 9 and sets the output element OR 7 unit, which sets the digital input unit gain K (t) for the analog signal on the second digital analog multiplier 2.

The synchronization pulses, arriving at the clock input of the digital generator of 3 functions, initiate at its output the digital binary codes of the variable gain factor K (t) at discrete points in time. These codes are written to the buffer register 5 according to the signal from synchronization unit 9. These codes, arriving at the digital inputs of the first digital-analog multiplier 1, set in it a variable gain factor K, (t Output signal 1 ,, of the device is equal to

 Century

Th .. l., - K, (t) -K, (t), (1)

where ig, is the input to the device. In this case, in the initial time interval, while the condition

K (t) K,

(2)

, ""

where K is the boundary gain factor of multiplier 1, the equalities are

K, (t) K (t) 1

K (t)

With K (t)

by formula

(3) (4) (5)

the element NOT 6 is triggered, on it. The output is set to a zero signal, which closes the AND 8 element to pass a synchronization pulse to record new codes in buffer register 5. The latter records the code corresponding to the value of the coefficient in the digital-analog multiplier 1. The output signal of the HE 6 also opens a group of 4 keys through which the signal From the digital generator 3, the functions are fed to the control inputs of the digital-analog multiplier 2, and the control signal is fed to the second digital-analog multiplier shifted. At the same time, the gain of the second digital-analog multiplier 2 is determined by analog input

loi

K / O -

3

(6)

by formula

Where

g is the number of bits of the buffer register 5.

mule

Using a K multiple of two,

by formula

you can always find such r to

 by formula

45

(7)

Substitute

we have

(eight)

50

55

Thus, the variable code (8), entering on the digital control, the input of the digital-analogue multiplier 2, sets the output signal of the device equal to

1v, and) lB.-. K, (t)

one

BX

K (t)

 one.

K (t)

(9)

In the considered device, the impulse noise in the output signal of each multiplier, created by switching the codes on its digital input, is not amplified by another multiplier. Indeed, in the initial interval, when condition (2) is satisfied, and consequently, conditions (3), (A), impulse noise in the output signal of the digital-analogue multiplier 1 with a factor of one passes to the output of the device. In the second time interval, i.e. when the gain in the second digital analog multiplier 1 is greater than one, in the first multiplier the pulse noise in its output signal is not generated, because the code switches on it. no digital input. In this case, at the output of the entire device, there are unamplified interference from switching codes only at the digital input of the second digital-analogue multiplier.

Thus, the use of blocks 4–9 made it possible to reduce the amplitude of impulse noise at the output of the device by a factor of K (t) and thereby increase the scaling accuracy.

Claims (1)

Invention Formula An analog-digital device for variable scaling, containing a digital function generator, connected by a clock input to the first output of a synchronization unit, and two digital-to-analogue multipliers, the first Compiled by S.Kazinov Editor M.Kelemesh Tehred L.Serdyukova Proofreader L.Patay Order 3584/51 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 5 5 about 0 five one of which is connected to an analog input with a scalable signal input of the device, and an output to an analog input of a second digital-analog multiplier, the output of which is an output of the device, characterized in that, to increase accuracy by reducing the amplitude of impulse noise, an element is NOT introduced , AND element, OR element, group of keys and buffer register connected to the zero input to the device start input and zero function digital input, buffer record write enable input connected to the output of the AND element, information inputs connected to the outputs of the low-order bits of the digital function generator (where r is the buffer register), the outputs of the g bits are at the digital inputs of the first digital-analog multiplier, and the output of the r-th bit is at the input of the NOT element and the control inputs of the group keys, the information inputs of which are connected to the outputs of all the bits of the digital function generator, with the exception of its gth bit, while the second output of the synchronization unit is connected to the first input of the And element connected second m input to an output of NOT circuit and the first input of the OR gate, a second input connected to the output of the ith discharge digital function generator and an output of OR and outputs key group are connected to inputs of the second digital-analog multiplier.