SU1487065A1 - Functional converter - Google Patents

Description

The invention relates to computing technology, in particular to devices for calculating functions, and can be used in a computer as a coprocessor for calculating arbitrary functions or as an independent device. The invention relates to computing equipment, in particular to devices for calculating functions, and can be used in a computer in as a coprocessor for calculating arbitrary functions or as a separate device in digital automatic control systems.

The purpose of the invention is to reduce hardware costs.

The drawing shows a block diagram of the Converter.

The functional converter contains a register of 1 argument, inputs of 2 arguments, a group of elements OF, a group of elements OR 4, an element AND 5,

2

device in digital automatic control systems. The aim of the invention is to reduce hardware costs. The functional converter contains the argument register, the setting inputs of which are the information inputs of the device, the AND element group, the OR group of elements, the four AND elements, the index register, the OR multiple input element, the two OR elements, the NOT element, the associative memory block, the function memory value block, trigger, T-flip-flop, mask register, priority encoder, digital outputs, initial setup input, synchronization input. The proposed function generator reduces hardware expenses due to the decrease in the number ¹ stored in the memory of the values. 1 ill., 1 tab.

index register 6, multiple entry element? OR 7, the element OR 8, the element is NOT 9, the element AND 10, the element OR 11, the element AND 12, the block 13 of the associative memory, the block 14 of the memory of function values, 0-trigger 15, the element AND 16, T-trigger 17, register 18 masks, priority encoder 19, outputs 20 ί of the converter, input 21 of the initial setup of the converter and input of 22 pulses of the converter.

The converter works next ’

shimm way.

In the initial state in block 13

the associative memory contains discrete values of the argument, and in block 8 of C 1487065 A1

1487065

four

ke 14 function values are the corresponding function values, and the quantization is carried out so that the interval between any neighboring function values is the same. For example, when reproducing the function £ (x) = x ² with an accuracy of 1 in the interval from 0 to 10, the information in blocks 13 and 14 of the memory corresponds to that given in the table.

Cell 13 memory block 14 memory cells 0.000 0,000 1,000 1,000 1,414 2,000 1.732 3,000 2,000 4,000 2.236 5,000 2.449 6.000 2.646 7.000 2.828 8.000 3,000 9.000 3.162 10,000

If it is necessary to calculate the function, the code of the argument is supplied to the information inputs 2 of the device. At the same time, a single signal is fed to the input 21, the rotor receives the code in register 1 of the argument, writes the mask register and the low order index register 6 units to all bits of register 18, and zeros to all other bits of register 6, and also sets the три-trigger 15 in one state, and T-trigger 17 - in zero.

After that, among the codes recorded in block 13 of the associative memory, the search for the nearest larger one to the number specified in register 1 of the argument is performed. When such a number is found from block 13 of the associative memory, its address is read, and at this address the value of the function corresponding to the number found is read from memory block 14.

The search for the closest one to the specified search argument occurs as follows. The first interrogation of block 13 of associative memory is carried out by code stored in register 1 of the argument, which is fed to the information input of block 13 of associative memory through a group of elements OR 4. At the same time, the code stored in register 18 is fed to the masking inputs

masks, and from the direct output of the 0-flip-flop 15 through the element OR 11 and the open element And 12 to the resolution input of block 13 receives a single signal allowing the search. Thus, when the first clock pulse arrives at the input 22, the first poll of the block 13 of the associative memory is performed. If the required number is not found, then at the output of the coincidence signal of the block 13 a zero potential appears, with the help of which the три-flip-flop 15 at the trailing edge of the sync pulse is set to zero zero and opens the elements 10 and 16.

Further search is carried out depending on the value of the low-order code of the argument. If it is equal to zero, then the block 13 of the associative memory is interrogated with the inversion of this digit, and, if the desired number is not found, the contents of the index register 6 and the register 18 of the mask are shifted. If the low order digit of the argument code is equal to one, then the contents of the index register 6 and register 18 are shifted,

This happens as follows. If the low-order digit of the argument code is zero, then the output of the element OR 7 appears a zero signal, which is inverted by the element NOT 9, the Single signal from the output of the element NOT 9 is fed through the open element AND 10 to the information input T-flip-flop 17, as well as the element OR 11 and the open element And 12, allows polling block 13 associative memory. At the same time, all the bits of the argument code, with the exception of the youngest, are fed to the inputs of block 13, instead of which one comes from element AND 5 and element OR 4.. Thus, upon the arrival of a sync pulse. the resolution of the block 13 of the associative memory is carried out and, on its trailing edge, the T-flip-flop 17 switches to a single state. The zero signal from the inverse output of the T-flip-flop 17 closes the AND 10 element to pass the associative interrogation permission signal in the next clock cycle, and a single signal from the direct output, passing through the OR 8 element and the AND 16 element, enters the shift control input of the mask register 18 and the input index register shift control1487065

6. When the next clock signal arrives, the contents of the registers 6 and 18 shift to the higher digits and the T-flip-flop 17 switches to the zero state.

If the low-order digit of the argument code is equal to one, then a single signal appears at the output of the multi-input element OR 7, which, passing through the element OR 8 and the open element AND 16, allows the shift of the index register 6 and the register 18 of the mask. Upon receipt of the next clock pulse, the contents of the registers 6 and 18 are shifted towards the higher bits. The issuance of the signal of the resolution of opt dew in the block 13 of the associative memory does not occur.

Processing the subsequent bits of the OSU · is carried out similarly, depending on their content. In this case, all scanned digits are masked when polled with zeros stored at the corresponding positions of the mask register 18, and the position of the digit being processed is indicated by a unit in the index register 6.

Such a survey continues until a unit appears on the signal output of the matching block of the associative memory 13, which indicates that the closest to the specified search argument has been found, and allows the function memory 14 to issue a function code. In this case, the I-trigger 15 on the trailing edge of the sync pulse is switched to one state. At the same time, at the output of the block of · 13 associative memory, signals appear that mark the position in block 13 of the numbers found and arrive at the encoder 19, If two or more numbers, t, e, meet the search criterion during polling. several single signals appear on the output; the encoder 19 selects the first one. Thus, if in block 13 of the associative memory an ordered array of numbers is written, then at the output of the encoder 19, the address nearest the larger to the specified search argument appears. After that, the value of the function is read from the memory block 14 at the found address.

Claims (1)

Claim Function converter containing the argument register, block the memory of the function values and the group of elements AND, the information input of the register of the argument is connected to the input of the argument of the converter, the output of the memory block of the function values is connected to the output of the converter, so that, in order to reduce hardware costs, it contains an index register, masks, associative memory block, T-flip-flop, приорит-flip-flop, priority encoder, element NOT, group of elements OR, four AND elements, two OR elements, multi-input OR element, with the outputs of the bits of the register of the argument connected to n rvymi respective inputs of the AND elements and the group or groups of bits from the first outputs io (n-1) th index register (where η - number of argument bits) are connected to second inputs respectively of the first through. (n-1) -th element OR group and elements AND group, the output of the η-th digit of the index register is connected to the first input of the first element AND and the second input of the η-th 'element AND group, the output of the first element And is connected to the second input n ~ The element OR of the group, the outputs of the elements AND of the group are connected to the corresponding inputs of the multi-input element OR, the output of which is connected to the first input of the first element OR and the input of the element NOT, the output of which is connected to the first inputs of the second element AND and OR, the outputs of which are connected respectively to the information input of the T-flip-flop and the first input of the third element And, the second input of which is connected to the inverse output of the три-trigger, the direct output of which is connected to the second input of the first element OR, the output of which is connected to the first input of the fourth element And, the second input of which is connected to the second the input of the first element And, the second input of the second element And and the inverse output of the-flip-flop, the direct output of which is connected to the second input of the second element OR, the output of the third element And is connected to the resolution input of the associative memory block, Ion input coupled to the outputs of the elements or a group of the fourth output element and connected to the control input of the index register and a shift control input of shift 1487065 the mask register whose output is connected to the masking input of the associative memory block; the output of the coincidence signal is connected to the information input of the P-flip-flop and the resolution input of the function’s memory block whose address input is connected to the output of the priority encoder whose input is connected to the information the output of the block of associative memory, the input clock of the converter is connected to the synchronization inputs of the index register, mask register, T-flip-flop,-flip-flop and block of associative memory, the initial input This is connected to the enable input of the record of the argument register, the installation inputs of the mask register, index register, T-flip-flop and ϋ-flip-flop. I am 2- [ 2.1 2.n-1 ~, O — A LL E & - $ £ ~ ΐ Yer 22 oh Ty m · hell 17. \ * —YU20.p