JP2976610B2 - Offset / Drift Compensation Circuit for D / A Converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset / drift compensation circuit for a D / A converter.

[0002]

As a conventional D / A converters of this kind, if example be through a pulse density modulation operation of the digital data, what as shown in the circuit diagram of FIG. 3 is known that configuration . 3, 1 is a pulse density modulator for outputting a rectangular waveform pulse density modulated signal having a duty ratio corresponding to the data S _d as input digital data S _d (D input), the data S _d a data latch DL ₁ to synchronize the clock signal CLK and the data latch DL ₂ to synchronize last added data in said signal CLK, adder for adding the output data of the both data latch DL ₁ and DL ₂ and ADD, the data latch DL ₃ for synchronizing the signal CLK and an addition data and carry signals of the ADD, and a the input signal inverting element NOT. Reference numeral 2 denotes an output buffer amplifier that outputs the signal _Vb using the pulse density modulation signal as an input signal, 5 denotes a low-pass filter that demodulates the output signal _Vb into an analog signal, and 4 denotes the pulse at a duty ratio of 50%. desired signal S _a of the intermediate value obtained by subtracting the analog signal from the output of the low pass filter value of said analog signal as a set value S _{the as} corresponding to the density modulation signal zero and make the positive and negative deflection
(D / A output). Incidentally resistance R ₁ of the set value S _{the as} the control constant voltage V _s
And R ₂ as a divided voltage.

Hereinafter, the operation of the pulse density modulator 1 will be described as follows.
A description will be given by taking a bit pulse density modulator as an example. Note that the input data is from 00 to 0F (hex), and the cycle of the operation clock signal CLK is T. Now, input data is 1
In the case of, the adder ADD accumulates one by one and the period is 16
Obtain T pulse output. Further, when the input data is 2, the data is similarly multiplied by 2 to obtain a pulse output having a period of 8T.
Furthermore, for example, when the input data is 8, the pulse data are similarly integrated by 8 to obtain a pulse output having a period of 2T and therefore a duty ratio of 50%. The pulse density modulated signal modulated as described above is output through the output stage buffer amplifier 2,
The signal is further demodulated by a low-pass filter 5 into an analog signal.

[0004]

The linearity of the D / A conversion in the D / A converter having the circuit configuration illustrated in FIG. 3 depends on the characteristics of the output stage buffer amplifier 2. Figure
4 is an output signal V _b of the output stage buffer amplifier 2
It is illustrative of the operation waveform diagram, and FIG. 5 is output signal V _b
The digital data S _d (D / A output) of the required positive / negative swing analog signal S _a (D / A output) obtained by subtracting the zero set value S _as from the analog output demodulated by the low-pass filter 5 which receives FIG. 9 is an example of a characteristic diagram corresponding to (D input).

As shown in FIG. 4, when a rectangular wave having a voltage value V _H and a time width t ₂ -t ₁ is input to the buffer amplifier 2, an output waveform is distorted from the rectangular wave, and the voltage rising speed is increased. And the voltage falling speed is different, resulting in an area difference as shown by the hatched portion in the figure. The voltage value _VL is an offset voltage when the buffer amplifier 2 is not input, and the voltage value V _L
HO is the sum _VH + _VL of the two voltages. The area is S
Shown hatched portions to _H and S _L may act as an addition component and subtraction component to the area of each of the rectangular wave, the distortion wave output of the buffer amplifier 2 the integrated value of the input signal to the low pass filter 5 which forms an output value the difference S _H -S _L of both areas such as in the strain wave if the input is to be output as a conversion error of the analog signal S _a of the digital data S _d a. Said differential area S _H -S _L becomes maximum when the output modulated signal of the pulse density modulator 1 is its duty ratio of 50% corresponding to the data S _d, the output value of the analog signal S _a when this zero As the signal S _a
The When forming the positive and negative deflection signal, the offset constituting the error in to the D / A converter corresponding to the area difference is the maximum value V _off at the zero point as shown in FIG. The dotted line near the zero point in FIG. 5 shows an ideal linear characteristic when the D / A conversion error is zero. Although the offset greatly depends on the characteristics of the buffer amplifier due to its generation as described above, the characteristics of the amplifier itself change due to fluctuations in the ambient temperature or the control power supply voltage, and the offset of the resistance giving the zero set value. since the characteristics of the pressure circuit is also changed by the temperature characteristic of the change or resistance of the control power supply voltage, wherein for linearity of the D / a conversion characteristic between the input data S _d and the analog signal S _a and its zero point position Drift occurs due to the influence of the control power supply voltage fluctuation or the ambient temperature fluctuation.

[0006] Compensation for the above-mentioned offset between D / A conversion error caused by the drift or the like has not been made, in a conventional D / A converter such as illustrated in FIG. Above view invention, the analog signal S _a digital data S _d may be performed using a simple circuit configuration improvements to the retention of linearity and its zero point position of the D / A conversion characteristic for D / A converters of It is intended to provide an offset / drift compensation circuit.

[0007]

In order to achieve the above object, an offset / drift compensation circuit of a D / A converter according to the present invention uses digital data as an input signal and outputs a pulse density modulation signal corresponding to the input signal. A pulse width modulation circuit or a pulse width modulation circuit that outputs a pulse width modulation signal corresponding to the input signal; a first output stage buffer amplifier that receives the pulse density modulation signal or the pulse width modulation signal as an input; In a D / A converter comprising an output signal of a buffer amplifier as an input and a first low-pass filter for demodulating the output signal into an analog signal, a clock signal of the modulation circuit is input and the analog signal is converted into a signal having both positive and negative swings. A frequency divider for outputting a modulation signal having a duty ratio corresponding to the digital data corresponding to the zero point in the case; A second output stage buffer amplifier having the same output characteristics as the first output stage buffer amplifier, and the second output stage when the low-pass filter is the first output stage. A second low-pass filter which receives the output signal of the stage buffer amplifier as an input, has the same characteristics as the first low-pass filter, and demodulates the input signal into an analog signal; and outputs the output of the second low-pass filter to the first low-pass filter. A differential amplifier for subtracting from the output of the low-pass filter or a differential filter circuit that receives the output signals of the first and second output stage buffer amplifiers as inputs. The output signal is used as a required analog signal.

[0008]

The conversion error of the D / A converter is determined by the pulse density modulation signal or the input signal of the demodulation unit when a cascade connection of a pair of buffer amplifiers and a low-pass filter is used as the demodulation unit. The pulse width modulation signal changes so as to become maximum when the duty ratio is 50%, and drift occurs under the influence of control power supply voltage fluctuation or temperature fluctuation. In the present invention , a digital data modulation section clock signal of the converter is input to a divide-by-2 circuit to obtain a modulation signal having a duty ratio of 50%, and the modulation signal is converted to the first demodulation section by the demodulation section.
In addition to the second demodulation unit having the same configuration and the same characteristics as the demodulation unit of
By making the result obtained by subtracting the output of the second demodulation unit from the output of the first demodulation unit a required analog output signal,
When the analog output value corresponding to the modulation signal having a duty ratio of 50% is output as a signal having both positive and negative swings that becomes zero, offset compensation of a zero point in the analog output signal is automatically performed.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are a circuit diagram and a D / A conversion characteristic diagram showing an embodiment of the present invention, respectively. In FIG. 1, components having the same functions as those in the embodiment of the prior art shown in FIG. 3 are denoted by the same reference numerals. Figure 1
In the circuit shown in 3, the resistor R ₁ and a set value for making the positive and negative deflection signal a constant voltage V _s consists R ₂ Metropolitan divide with zero intermediate value the analog output signal S _a of the S
_As an alternative to the resistor divider circuit that provides _as , the frequency divider circuit 71 that receives the clock signal of the D / A converter and outputs a modulation signal having a duty ratio of 50%, receives the output of the divider circuit as an input, and outputs the buffer amplifier 2 And a buffer amplifier 72 having the same characteristics as the above, and a low-pass filter 6 which receives the output of the compensation circuit as an input and has the same characteristics as the low-pass filter 5, and outputs the output of the filter 6 to a differential amplifier. 4 are those in which none the required analog signal with a analog signal S _a result of subtracting the output of the filter 5 via, those forms always zero analog output value corresponding to the duty ratio of 50% of the modulation signal is there.

[0010] FIG. 2 is a D / A conversion characteristic diagram of the circuit of Figure 1, in a case that forms the zero value of the analog signal S _a which corresponds to the digital data S _d of the duty ratio of 50%, the analog signal S The offset V _off at the zero point of _a is automatically compensated for, including its drift, to secure the position of the zero point.

[0011]

According to the present invention, a digital-to-analog (D / A) converter converts digital data into an input signal, converts the input signal into a pulse density modulation signal or a pulse width modulation signal, and demodulates the analog signal through a buffer amplifier and a low-pass filter. A frequency dividing circuit for outputting a modulated signal having a duty ratio corresponding to data corresponding to a zero point when the clock signal of the converter is input and the analog signal is converted into a positive and negative swing signal; and the frequency dividing circuit. And the second input signal having the same input / output characteristics as the first buffer amplifier.
And the low-pass filter is connected to the first
A second low-pass filter having the same characteristics as the first filter and demodulating the input signal into an analog signal; and a differential for subtracting the output of the second filter from the output of the first filter. By providing an amplifier and converting the output signal of the differential amplifier into a required analog signal, it is possible to automatically compensate for the offset at the zero point of the analog signal and its drift.

Further, by forming the pulse density modulation circuit or the pulse width modulation circuit as a digital circuit and incorporating it in a gate array, the circuit configuration can be made compact and inexpensive.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing D / A conversion characteristics in the circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing an embodiment of the prior art.

FIG. 4 is an operation waveform diagram of the circuit shown in FIG. 3;

FIG. 5 is a diagram showing D / A conversion characteristics in the circuit shown in FIG. 3;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 pulse density modulator 2 buffer amplifier 4 differential amplifier 5 low-pass filter 6 low-pass filter 7 zero compensation circuit 71 2 frequency divider 72 buffer amplifier ADD adder DL ₁ data latch DL ₂ data latch DL ₃ data latch NOT input signal inverting element R ₁ resistance R ₂ resistance

Claims (1)

(57) [Claims] A pulse density modulation circuit that outputs digital data as a pulse density modulation signal corresponding to the input signal or a pulse width modulation circuit that outputs a pulse width modulation signal corresponding to the input signal; A D / A converter comprising: a first output-stage buffer amplifier to which a pulse density modulation signal or a pulse width modulation signal is input, and a first low-pass filter to which an output signal of the buffer amplifier is input and demodulated into an analog signal. In the modulation
The clock signal of the circuit is input and the analog signal is positive or negative
The digital equivalent of the zero point when both shake signals are used
Output the modulation signal with the duty ratio corresponding to the data
A frequency dividing circuit, and an output signal of the frequency dividing circuit as an input, and
A second output having the same characteristics as the first output stage buffer amplifier.
Power stage buffer amplifier and the second output stage buffer amplifier
And the first low-pass filter
A second low-pass filter having the same characteristics as
The output of the low-pass filter in the first low-pass filter.
A differential amplifier for subtracting from the output of the
The output signals of both output stage buffer amplifiers
A differential filter circuit for converting the output signal of the differential amplifier or the differential filter circuit into a required analog signal.
Drift compensation circuit.