SU1374253A2 - Voltage multiplier - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in analog computers. The aim of the invention is to improve accuracy and speed. The device for multiplying voltages contains the first and second pulse-width modulators 1 and 2, the unequal element 3, the low-frequency filter 4, the inputs 5 and 6 of the first and second signal multipliers, the output 7. The second pulse-width modulator 2 contains the first and second large-scale resistors 8 and 9, the operational amplifier 10, the integrated- handler. capacitor 11, D-flip-flop 12. The device is based on converting the first and second signal multipliers into pulse-width modulated pulse signals, received in the second pulse width modulator 2 using D-flip-flop 12 positive and negative edges of the pulse signal is synchronized with the fronts of one polarity of the signal from the output of the first pulse-width modulator 1..2 Il ,. (L

Description

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The invention relates to electrical computing devices and can be used in analog computers.

The purpose of the invention is to increase accuracy and speed.

FIG. Figure 1 shows a functional diagram of a device for multiplying voltages; in fig. 2 - time diagrams of signals.

The device contains first and second pulse-width modulators 1 and 2, unequal element 3, low frequency filter 4, input 5 of the first signal-multiplier, input 6 of the signal-multiplier, output 7, first and second large-scale resistors 8 and 9, operational amplifier 10, integrated capacitor 11, B-trigger 12, zero potential bus 13, third, fourth, five and sixth resistor resistors 14-17, additional operational amplifier 18, additional integrating capacitor 19 charging resistor 20 and storage capacitor 21.

The device for multiplying voltages operates as follows.

The input 5 is supplied with the first signal-factor in the form of voltage, to the input b - the second signal-factor as current. The first multiplier signal in the first pulse-width modulator 1 is converted into a pulse duty cycle, which is fed to the first input of the unequal element 3. On integrating capacitor

11 a voltage change occurs, determined by the currents flowing through the first large-scale resistor 8

and a second large-scale resistor 9. At the time when the voltage is zero on the inverting capacitor 11 at the output of the operational amplifier 10, which functions as a capacitor, the voltage varies in sign. The charge of the integrating capacitor 11 in this case occurs with the same current. At the moment of the next positive edge of the Signal from the output of the first pulse-width modulator 1 D-flip-flop

12 changes its output signal in accordance with the output of the operational amplifier 10. At this point, the voltage on the integrating capacitor 11 begins to decrease. When the zero level is reached, the voltage at the output of the operational amplifier

10 takes the initial value. The voltage change at the output of the L-trigger 12 occurs at the next

positive front of the output sig

The first pulse width modulator 1. So, the pulse ratio at the output of the second pulse width modulator 2 is proportional to the signal at its input with some approximation.

The conversion period of the second pulse-width modulator 2 is not a constant value, but

determined by the conversion period of the first pulse-width modulator 1 and the magnitude of the second multiplier signal from input 6. The second multiplicative signal from input 6 is converted

in the second pulse-width modulator 2 into a stream of pulses, the positive and negative edges of which are synchronized by the fronts of one polarity of the signal from the output of the first

pulse width modulator 1.

FIG. 2 are designated: a - signal at the output of the first pulse-width modulator 1J b - signal at the inverting input of the operational amplifier 10; in - the signal at the output of the second pulse-width modulator 2; г- сна.нал at the exit of the element 3 unequal; d - output signal 7; TVJ is the averaging time determined by

filter 4.

In the proposed device, in the case of irrational values of the first and second signal-factors, the methodical error is inversely proportional to the time of averaging, and in the known device it is much slower. Due to this, higher accuracy of the operation of the proposed device is provided.

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Claims (1)

Invention Formula A device for multiplying voltages according to auth.St. No. 1159037, in order to improve accuracy and speed, the second pulse-width modulator is made on an operational amplifier, the first plate of the integrating capacitor and the first steps of the first and second large-scale resistors are connected to the non-inverting input the first scale resistor is the input of the second pulse-width modulator, the second plate of the integrating capacitor is connected to the zero potential bus, the output of the operational amplifier is connected to the information input of the D-flip-flop, the output of which is connected to the second end of the second large-scale resistor and is the output of the second width-width modulator, clock input D -trigger connected to the output of the first pulse-width modulator. C} and. 2