SU1633383A1 - Multi-channel device for information input - Google Patents

Abstract

The invention relates to computing and can be used in information-measuring systems and devices for digital signal processing. The purpose of the invention is to improve the accuracy of the device. The invention relates to computing and can be used in information-measuring systems and in digital signal processing devices. The aim of the invention is to improve the accuracy of the device. Figure 1 shows the structural diagram of the device; 2 is a block diagram of the control block,. on va. The goal is achieved by the fact that a second multiplexer, as well as the first multiplexer 4, the register 5, and the control unit 6, are introduced into the device containing n channels 1i of the analogue information lane, each of which contains a block 21 of analog memory and an analog-digital converter 31 9 and digital-to-analog converter 10, and in each channel 11 for inputting analog information — adder 71 and integrator 81. The accuracy of the multi-channel input device is improved by frequency separation of the useful interference signal. The correction of the interference signal is carried out independently of the main signal and occurs simultaneously with the operation of the information conversion channel. The use of a correction loop in the low-frequency region of the channel transfer characteristic eliminates the bias voltage error of the analog blocks of the information conversion channel and thereby improves the accuracy of the device. 3 il. o (L fig.Z - time diagram of the device operation. The multichannel input device of narrowband signals contains n channels of analog information input (), each of which contains an analog memory block 2 and an analog-digital converter 3, multiplexer 4, register 5 and control unit 6, and in each channel there is a supplement

Description

the body is an adder 7 and an integrator 8, the device additionally contains a second multiplexer 9 and a digital-analog converter 10 “

In the control unit 6, the output of the clock generator 11 is connected to the first inputs of the first 12 and second 13 I circuits, the second inputs of which are connected respectively to the forward and inverse outputs of the trigger 14, the output of the first I circuit 12 is connected to the counting input of the first counter 15, the outputs of which connected to the inputs of the first decoder 16, and the output of the second circuit AND 13 is connected to the counting input of the second counter 17 and through the delay line 18 and the driver 19 enters the output of the control unit 6 on the bus. Write to the operational memory First output of the first decoder 16 is the first output of control unit 6, the second output of the first decoder 16 is the second output of control unit 6, and the third through the second driver 20 is connected to the setup input of the trigger 14, the unit input of which is connected to the installation inputs of the first 15 and second 16 counters, with counting the input of the third counter 21 and connected to the output of the third driver 22, the input of which is connected to the output of the third circuit AND 23, the first input of which is connected to the output of the second decoder 24, and the second is the control input of the control unit 6 occurrence. The output of the second counter 17 is the output bus of the address of the control unit 6, and is also connected to the input of the second decoder 24 and to the first input of the code matching circuit 25, the output of which is the third output of the control unit 6, and the second input is connected to the group of higher-order bits The third counter 21, which simultaneously is the second output bus of the address of the control unit 6, is located.

The device works as follows.

If there is a permit potential at the control input of the control unit 6 (Fig. 3), a sampling control pulse is generated at its first output by the analog memory block 2 simultaneously on all the input channels of the analog information. The level of the analog signals is sampled on all channels.

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the signals arrive at the inputs of blocks 2 through adders 7 in each channel, where a constant voltage equal to the voltage of the conversion path offset given to the input is added to the narrow-band input signal, but with the opposite sign

After completing the sampling procedure from the second output of control unit 6, a trigger signal for analog-digital converters is generated, which is fed to the control inputs of all analog-digital converters 3 simultaneously of all analog information input channels. After the coding procedure on the output address bus of control block 6, they start to form channel addresses of a multi-channel input device. These addresses control multiplexer 4, which sequentially connects the outputs of analog-digital converters 3 analog data input channels to the output data bus of the device. At the same time, control unit 6 generates a sync pulse of the channel address on the output address bus and data-. on the channel on the output bus data-. Thus, the data reading procedure is carried out. After the reading procedure, the cycle of operation of the device is repeated with

In parallel with the data conversion and reading mechanism for channels, the offset error correction mechanism operates. The essence of the offset error correction mechanism operation is as follows: Address to the second address bus of the control unit 6 second multiplexer 9 connects the output of the digital-analog converter 10 in series to the integrator inputs 8 in the input channels analog information. Moreover, the connection time of each channel significantly exceeds the cycle of the conversion and input device For example, during the connection of the integrator 81 of the 1st channel, no less than 1024 encodings according to Kanajry should be implemented. Simultaneously, from the third output of the control unit 6, data is written to the register 5 only from that output. channel, the integrator of which is currently connected to the output of the second multiplexer 90. Thus, you

The currently used input channel for analog information on the address on the second address bus of control unit 6 is for some time covered by negative feedback through the digital-to-analog converter 10 and integrator 8 of the channel. Implementing this feedback eliminates the offset error at low frequencies connection, t0e0 reduce it to the level of error of the D / A converter 10 and the integrator 8, But since the circuit operates at a low frequency, it allows to achieve a high level This allows a significant reduction in the requirements for broadband nodes in terms of the stability of the bias voltage in the analog input channel, t, e "to adder 7, block 2 of analog memory and analog-to-digital converter 3

The second multiplexer 9 sequentially in time connects the inputs of the integrators of 8 different channels of input of analog information to the output of the digital-to-analog converter 10. Signal. the third output of the control unit 6 is generated at such a moment of the reading cycle that register 5 records the data of the analog input channel that is currently in the correction state. The same channels that integrators 8 are currently off the second multiplexer, U, stores at the inputs of the adders 7 the amount of corrective -parameter, since the integrators with the inputs disabled are in this case playing the role of analog storage devices. According to the number of channels of the multichannel analog information input device, the frequency of the corrected bias voltage is reduced.

The multichannel correction circuit does not affect the frequency bandwidth of the analog information input channels, which contains the frequency spectrum of narrow-band analog signals converted by the device. Therefore, the conversion and correction procedures proceed independently from each other and at the same time.

 Control 6 works as follows.

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The generator 11 operates continuously and after the input of the open signal to the reset circuit AND 23 of the first 15 and second 17 counters, respectively, and the installation of the trigger 14 initially begins to fill the first counter 15 via the first AND 12 circuit. From the output of the first counter 15, the first decoder 16 generates signals the first and second outputs of the control unit 6, and through the driver 20 - the reset signal of the trigger 14 after resetting the trigger 14 through the second circuit AND 13 from the generator 11, the second counter 17 begins to fill up, the output of which addresses of polling channels in the reading procedure About From the output of the second circuit AND 13 via delay line 18 and shaper 19 each polled address is accompanied by a sync pulse of writing data to the operational memory. The end of the address polling field of the channels is detected by the second decoder 24, the output of which is via the third circuit And 23 and the shaper 22 resets the registers 15 and 17, sets the trigger 14, and also writes the unit to the third counter 21 "T of this moment, the new cycle of the device operation begins

The third counter 21 counts1 the number of device operation cycles. The older bits form the second output address spike of the control unit 6, which determines the connection sequence of the device drops} into the correction mode0 Circuit 25 matching codes, the inputs of which receive the addresses of the polled channel in the read mode and addresses to: the shala, which is in the correction mode, generates at its output a clock signal writing data words to the register of the digital-to-analog converter of the reverse draw circuit „

Claims (1)

Invention Formula A multi-channel information input device containing a first multiplexer, a register, a control unit, and in each channel an analog memory block, an analog-to-digital converter, whose information input is connected to the output of the analog memory block, the first output of the control block is connected to control 1dm inputs a block of analog memory, the second output of the control unit is connected to the start inputs of analog-digital converters, the outputs of which are connected to the information inputs of the first multiplexer, whose address inputs They are connected to the outputs of the first group of the control unit and are the address outputs of the device, the start input and the synchronous input of which are, respectively, the input and the fourth output of the control unit, the outputs of the first multiplexer are information outputs of the device, increase the accuracy of the device, a second multiplexer, a digital-to-analog converter, is introduced into it, and each channel additionally contains an adder and an integrator, The first inputs of the adders are the information inputs of the device, the outputs of the adders are connected to the information inputs of the corresponding analog memory blocks, the information inputs and the register clock input are connected respectively to the information outputs of the device and the third output of the control unit, the outputs of the register are connected to the inputs of the cisro-analogue converter, the output of which is connected to the information input of the second multiplexer, the address inputs of which are connected to the outputs of the second group of the control unit EIW second multiplexer outputs are connected to respective inputs of the integrators, whose outputs are connected to respective second inputs of adders Jf  l; ABOUT -L