SU1543570A1 - Device for a-d conversion of television signal - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to improve the accuracy of the conversion. The device contains an analog switch 1, a test signal generation unit 2, an A / D converter 3, an address generation unit 4, a correction value calculation unit 5, an AND 6 unit, a clock rm 7, a memory block 8, an adder 9 and a sync pulse regeneration unit 10 . The goal is achieved by providing a dynamic error correction. 4 hp f-ly, 2 ill.

Description

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The invention relates to television technology and can be used in television devices with digital signal processing.

The purpose of the invention is to improve the accuracy of the conversion by correcting the dynamic error.

Fig. 1 shows a structural electrical circuit of an apparatus for analog-to-digital conversion of a television signal; 2 shows timing diagrams for his work.

The device for analog-digital conversion of a television signal (Fig. 1) contains an analog switch 1, a test signal generation unit 2, an analog-digital converter (ADC) 3 an address generation unit 4, a correction value calculation unit 5, element 6, a clock generator 7 , block 8 of memory, adder 9, block 10 of regeneration of clock pulses.

The test signal generating unit 2 contains a digital-to-analog converter (D / A converter) 11, an adder 12, a first counter 13, a switch 1, a second counter 15

The address generation unit k contains a register 16 and an adder 17.

The correction value calculation unit 5 comprises a register 18 and an adder 19; Block 10 regeneration sync pulses contains a register 20, the element And 21 sync selector 22, the first 23 and the second 2 one-shot.

A device for analog-digital conversion of a television signal operates as follows.

In the time interval (figure 2, and

Inside the sync pulses of the input television signal (on the flat parts of the vertices of the sync pulses), the conversion errors are corrected, and in the remaining time intervals the analogue-digital conversion of the television signal is performed.

In the analog-digital conversion mode, the input television signal through the analog switch 1 is fed to the signal input of the ADC 3. The digital signal from the output of the ADC 3 is fed to the first input of the adder 9, which is summed with the correction signal coming from the memory block 8. Next, from the output of the adder 9 through the block 10 regeneration sync

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The pulses of the digital television signal are output to the device.

The correction signal is read from memory block 8 at the address corresponding to the instantaneous value of the signal from the output of the A / D converter 3 and its derivative, determined by the address generation unit k. The derivative of the output signal of the ADC 3 in block k is determined by subtracting in the adder 17 of block k from its current value of the output signal of ADC 3 its value in the previous series, which is achieved by delaying the current value of the output signal of ADC 3 by register 16 of block k for one clock cycle.

In this mode, clock pulses through AND 6 are blocked by a low level signal at its second input, as a result of which the correction table in memory block 8 is not updated and the test signal is generated by block 2.

In the conversion error correction mode, the device operates as follows. (

At time t1 (FIG. 2, a), the sync selector 22 of block 10 forms the leading edge of the sync pulse (FIG. 2, b), which launches the first single vibrator 23 forming the delay pulse (FIG. 2, c), with a delay determined by the duration the output pulse of the first one-shot 22, starts the second one-shot 2k, forming at its outputs two protuphase pulses (figure 2, d e), determining the time interval during which the conversion error is corrected (interval t2-t3, figure 2, a ). In this time interval, the first input prohibits the passage of clock pulses through the element 21 of block 10, resulting in the entire time interval at the output of the register 20 of block 10, the signal value corresponding to the time t-b

At the same time, at time tt, operation of block 2 and block 8 in the recording mode is permitted by allowing the clock pulses to pass through the IB element. In addition, analog switch 1 switches the ADC 3 input from the device input to the output of the test signal generating unit 2.

In each clock cycle (period of the clock generator 7), block 2 generates a certain value of the analog test signal, which is converted into digital form by the A / D converter 3. The output signal of the A / D converter 3 and the reference value of the test signal from the second output of block 2 are fed to the inputs of block 5 of the calculation

the value of the amendment, which measures the error of the g address, the unit for calculating the value of the transformation range. Registraction register 18, element I and regeneration unit

unit 5 serves to combine in time the compared (subtracted) adder 19 of unit 5 signals.

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From the output of block 5, the correction value is written to memory block 8 at the address generated in the same way as described for the analog-digital conversion mode of the television signal.

The formation of the test signal in block 2 is performed as follows.

Clock pulses from the output of the element 6 through the second input of block 2 arrive at the clock input of the second counter 15. The output code of its higher bits goes to the switch 14, through which it passes depending on the state of the lower bit of the counter 15 (its second output) ., i.e. Only the even (or odd) values of the output code of the counter 15 are passed to the output of the switch 14 without the least significant bit.

The transfer pulses of the second counter 15 are fed to the input of the first counter 13, the output code of which in the adder 12 of block 2 is summed with the output signal of the switch 14. When a transfer signal appears at the second output of the adder 12, the second counter 15 is reset.

The output signal of the adder 12 of block 2 is a test signal | in numerical form, which is fed through the DAC 11 to the third input of the analog switch 1 and to the input of the correction value calculator 5.

Claims (5)

1. Device for analog-to-digital conversion of a television CHI-nal containing a clock generator, the first output of which is connected to the clock input of the analog-digital converter (ADC), the output of which is connected to the first input of the adder and 20 25 thirty sync pulses, the signal input of which is connected to the output of the adder, the clock input is connected to the first output of the clock generator and the first input of the element I, the first output is the output of the device for analog-digital conversion of the television signal, and the second output is connected to the second input of the element And the first input of the analog switch, the second input of which is the input of the device for analog-to-digital conversion of the television signal, the third input is connected to the first output of the test generator signal, and the output is connected to the signal input of the ADC, the output of which is connected to the first inputs of the address generation unit and the correction value calculation unit, the second inputs of which are connected to the second output of the clock generator and the first input of the test signal generation unit, the second input of which is connected to the output 5 of the And element and with the second input of the memory unit, and the second output is connected to the third input of the correction value calculator, the output of which is connected to the third input of the memory block, 40 " whose fourth input is connected to output block address formation. 2. The device according to claim 1, wherein the test signal generating unit comprises a digital-analog converter (D / A converter), the output of which is the first output of the test signal forming unit CHI-pulse the DAC input is its first input, and the DAC signal input is the second output of the test signal generation unit and connected to the first output of the adder, the first and second inputs of which are connected respectively to the outputs of the first counter and switch, the input of the first counter is connected to the first output of the second sch Aetchik, the second and third outputs of which are connected to the corresponding 50 55 the first input of the memory unit, the output of which is connected to the second input of the adder, characterized in that, in order to increase the conversion accuracy by correcting the dynamic error, an analog switch, a test signal generating unit, a generating unit five 0 five 0 sync pulses, the signal input of which is connected to the output of the adder, the clock input is connected to the first output of the clock generator and the first input of the element I, the first output is the output of the device for analog-digital conversion of the television signal, and the second output is connected to the second input of the element And the first input of the analog switch, the second input of which is the input of the device for analog-to-digital conversion of the television signal, the third input is connected to the first output of the test generator signal, and the output is connected to the signal input of the ADC, the output of which is connected to the first inputs of the address generation unit and the correction value calculation unit, the second inputs of which are connected to the second output of the clock generator and the first input of the test signal generation unit, the second input of which is connected to the output 5 of the And element and with the second input of the memory unit, and the second output is connected to the third input of the correction value calculator, the output of which is connected to the third input of the memory block, 0 " whose fourth input is connected to output block address formation. 2. The device according to claim 1, wherein the test signal generating unit comprises a digital-analog converter (D / A converter), the output of which is the first output of the test signal forming unit CHI-pulse the DAC input is its first input, and the DAC signal input is the second output of the test signal generation unit and connected to the first output of the adder, the first and second inputs of which are connected respectively to the outputs of the first counter and switch, the input of the first counter is connected to the first output of the second sch tchika, second and third outputs are connected to sootvetstvuyu0 five The first inputs and the second inputs of the second counter are connected respectively to the second output of the adder and to the second input of the test signal generating unit. 3. The device pop. 1, which differs from the fact that the address formation contains the serially connected register and the adder whose first inputs are the first input of the address generation unit, the second input and output of which are the second register input and output adder. . A device according to claim 1, in which the bpoc for calculating the correction value contains serially connected registers and an adder, the output of which is the output of the computation block of the correction value, the first input of which is the second input of the adder, and the second and third inputs, respectively, the first and second inputs of the register. 5. The device according to claim 1, that is, that the sync pulse regeneration unit contains a register, the first input of which is the signal input of the sync pulse regeneration unit, and the output is its output and is connected via serially connected the sync selector, the first and second one-shot and the element I with the second register input, the second input of the element I being the clock input of the sync pulse regeneration unit, the second output of which is the second output of the second one-wave.