SU1548779A1 - Generator of number elements of multiplication table - Google Patents

Abstract

The invention is intended for use in digital signal processing devices, in particular, for the generation and reception of noise immunity codes. The aim of the invention is to simplify the generator of numerical elements of the multiplication table in a simple field of characteristic P. The generator contains clock inputs 1 and cycle pulses 2, counter 3, adder 4, driver 5 times pulses, register 6, comparison circuit 7, subtractor 8, sensor 9 numbers P, an element OR 10. The goal is achieved due to the fact that the generator contains a counter 3. 2 Il., 1 tab.

Description

tp

2

cl

4b

00

h j

with

refers to avtzmtrgke

6 9 7 pr sa a

ten

20

and computer technology and can be used in digital signal processing devices, in particular for generating and receiving error correcting codes.

The purpose of the invention is to simplify the generator of the numerical elements of the multiplication table in a simple field of characteristic p.

Fig 1 shows the functional 1 generator circuit; Fig 2 is an example of the generator operation.

The generator contains synchronizing inputs of clock pulses 1 and cyclic pulses 2, counter 3, adder A, driver of 5 multiple pulses, register 6, comparison circuit 7, subtractor 8, sensor 9 of p number, element OR 10 and output I1 „

The generator of the numerical elements of the multiplication table in a simple field of characteristic p works as follows.

At input 1, clock pulses are received with a follow-up period equal to the time between two adjacent columns of the multiplication table ,, At input 2, synchronizing cycle pulses are received with a follow-up period equal to (p-1) 2 clock periods TT "In one cycle, all consecutively (p-1) 2 non-zero numerical elements of the multiplication table. Once per cycle, the cyclic pulse at input 2 sets counter 3 to the zero state. The shaper 5 generates clock pulses from the clock pulses following with a period of T3 -1 / F3 T1 (p-1). After the installation, counter 3 starts counting the clock pulses received at input 1, and successively outputs the codes of the multiplication table column numbers equal to numeric non-zero elements of the first row of the table 1, 2 ,, ..., Ј.,, „., р-1. Codes arrive at the first input of the adder "to synchronize30

35

40

45

25

6 with the number p received from sensor 9. If 6jj t, p, the signal from the output of circuit 7 enters subtractor 8, which performs operation 6, -j-p-of .. Thus, subtractor 8 forms modulo p. If 6; p signal and signal

fi

j P

through the element

OR 10 are fed to the output 11 of the generator.

The operation of the generator as shown in FIG. The generator produces a periodic sequence of multiplication tables in a simple field of characteristic 7 with nonzero numeric elements.

3, 4,

five,

6 (table)

12,

one

3 5 6

Claims (1)

25 claims 0 five 0 five The generator of numerical elements of the multiplication table containing a multiple pulse shaper, an adder, a comparison circuit, a register, a chitter body, a ps number sensor OR element, characterized in that, for the sake of simplicity, it contains a counter, the counting input of which and the multiple pulse shaper input are connected to to the input of the synchronizing clock pulses of the generator “the input of the synchronizing cyclic pulses of which is connected to the installation input of the counter, the output of which is connected to the first information input of the adder, the second information onny input thereof and a first input of a comparison circuit connected to the outputs on the register, whose input is connected to the output of the adder, the clock input of which is connected to the output of the multiple pulses, the second input of the comparison circuit and the first information The input of which is fed to the subtractor is connected to the output pulses from the generator 5. The second input of the adder k receives the summation result obtained in the previous period Tj from the output of register 6, which stores the total number & - during one period T3. At the same time, register 6 gives the number b. in scheme 7 which compares the number 55 The p-number sensor, the output. Less comparison circuits are connected to the first input of the OR element, the second input of which is connected to the output of the subtractor, the second information input of which is connected to the output More or equal to the comparison circuits, the output of the OR element is connected to the generator output. input of the subtractor connected to the output Sensor number p, output A smaller comparison circuit is connected to the first input of the OR element, the second input of which is connected to the output of the subtractor, the second information input of which is connected to the output More or equal to the comparison circuit, the output of the OR element is connected to the generator output.