SU1309317A1 - Device for decoding reed-solomon codes - Google Patents

Abstract

The invention relates to computing. Its use in the equipment for processing and transmitting digital information allows to increase the speed of the device. A device for decoding Reed-Solomon codes contains an input unit 1, a buffer storage device 2, a polynomial calculating unit 3 of the generalized checks, a polynomial calculating unit 6 for error locators, a key equation solving unit 7, a correction unit 8, and adders unit 9. Introducing the input generator 4 of the Galois field elements and the input multiplier 5, as well as the corresponding execution of block 3, provides parallel processing of all the characters of the code word, which ends in the reception cycle of the last character. 2 Il. (L T 21 CO O CO CO Figure 1

Description

113093

The invention relates to computing and can be used in processing equipment and the transfer of digital information.

The aim of the invention is to improve the speed of the device.

FIG. 1 is a block diagram of an apparatus for decoding Reed-Solomon codes; FIG. 2 - a functional diagram of one section of a block for the computation of a generalized checks polynomial

A device for decoding Reed-Solomon codes contains an input unit 1, a buffer storage device 2, a generalized checks polynomial calculation unit J5 3, a generalized testing polynomial generator (WMOS), a Galois field element generator 4 GF (2), an erasure locator polynomial calculator 6 (VMLS), block 20 7 key equation solution (CGS), correction block 8 and block 9 adders.

Block 3 for calculating the generalized checks polynomial was performed on n – k odiac sections, where n is the total number of 25 characters of the word in the Reed-Solomon code, is the number of its information symbols. Each section has (FIG. 2) a first multiplier 10, a first summer 11, a register 12, a multiplier 13 by a constant, a second adder 14, a second multiplier 15, a third and fourth adders 16 and 17, a third multiplier 18, a Galois generator 19 elements GF (2).

The constant by which the multiplication of the multiplier 13 is multiplied is for the S-th section the S-th element B of the Galois field.

Blocks 1,2,6-9 are made the same, 0 as well as known. In addition, the device has inputs 20 and outputs 21.

All multipliers and adders are combination type circuits and are not synchronized: 45

Register 12 is executed on D-flip-flops and is synchronized with the clock frequency accompanying the input symbols. The generators 4 and 19 of the Galois field elements are feedback shift registers JQ ry. The width of the shift registers, as well as the gap of the multipliers, adders and registers is equal to a, and a and n are related by the ratio n 2 - 1.55

The generator is clocked with the same frequency as the register 12 of the section 3 of the block 3 for calculating the polynomial of generalized checks.

35

g

50

5 o

0

five

Q 5

five

172

A device for decoding Reed-Solomon codes operates as follows.

a-bit characters (n 2 - 1) from inputs 20 are fed to input block 1, which transmits characters belonging to the alphabet GF (2), to input of accumulator 2, and erase characters are replaced by zero and are also transmitted to input of buffer storage 2 In addition, block 1 generates erase locators, which are elements of the Galois field CF (2) and the numbers of incoming erase characters. The counting is conducted from the maximum element to the unit element, since the code polynomial is fed to the inputs 20 by the leading coefficients forward.

The erase locators are fed to the erase locator calculation unit 6 and to the multiplier 5.

Block 6, based on the erasure locators x, e Ij-O, where l) is the number of erasures, calculates the erasure polynomial and (z) using the formula

6 (z) P () 1+ 21 zS,

fr-1 5 1 5

gdeyd - Sth coefficient of a polynomial (S 1, d),

The coefficients of the erase locator polynomial, formed in block 6, are received in block 3 of the generalized checks polynomial calculation and in block 8 of correction, and block 3 uses all intermediate values of the coefficients 5 f () obtained in each i-th cycle, and in block 8 only the last values are used, i.e., (sn (S 1, d).

The multiplier 5 multiplies the elements of the GF (2) field generated by the generator 4 and the erase locators of block 1. The work is fed into block 3.

Block 3, based on the input symbols from product 1 from multiplier 5 and intermediate values of the erase locator polynomial coefficients from block 6, calculates the values of the coefficients of the polynomial for generalized checks. The following signals are sent to each S-th section of block 3 (Fig. 2): di is the input symbol from block 1; X Е - product from multiplier 5; E is the Sth element of a Galois field, a cone element for a cathd section (in multiplier 13), chd ,, g; values derived from the previous S-1 block section

313093

3) (intermediate values of the S-1-th coefficient of the erase locator polynomial, coming from block 6.

Each section of block 3 of the generalized checks polynomial calculates the values of the coefficient of the generalized checks polynomial using the formula

5--1

j

,, Ch. T5; -B-a; + a, 6, -, jB +

5-1g - 0 a, Z: 6, -,)

i-1

.

B + a.

The third multiplier 18 is supplied with an intermediate coefficient value of the erase locator polynomial e.

/ (T

and the Galois field element 1 is from generator 19. The result of the multiplication is added to the Igj value of the previous section and is fed to the input of the adder 16, where it is added to the unit constant, and to the input Ij. J of the next section The result of the addition is multiplied by the second multiplier 15 to the input symbol d and fed to the input of the second adder 14. The previous value Tjj of the coefficient of the generalized checks polynomial stored in register 12 is multiplied by a constant and multiplier 13 and fed to another input of the second adder 14 The q q output obtained at the output of the second adder 14 is transmitted to the first adder 11 The value of q — from the previous section is multiplied at the first multiplier 10 by the value that is the same for all sections, and is fed to another input of the first an adder 11 whose output is fed to the input of the register 12, the memory value Tj j in the next cycle. In the very first section, to the input of the first multiplier 10 instead of the missing signal q 5 (1 is fed, and instead of

fsi - O.

signals 6.. „-.

Thus, blocks 1-6 finish processing simultaneously with the reception of the last character of the code word. For the operation of blocks 7, 8, additional decoder clock cycles are needed. The number of extra clocks depends on the correcting ability of a particular code.

Block 7, on the basis of the coefficients of the polynomial TgjS} + P, d generalized checks, arrives at it, decides the key equation

. d + HlgZ. ) (z) and (z) mod,

93

0

 five

20 . 30 .. 35

17 four . where d is the number of corrected code symbols.

The result of the solution is a polynomial of error locators d (z) and a polynomial l (z).

Block 8, based on the coefficients of the polynomials T (z), d (z), d. (Z), 1, (z), coming from blocks 3, 6, 7, calculates the values of the corrections Y, summed up in block 9 with the delayed drive with 2 characters. The corrected symbols are supplied from block 9 to outputs 21.

Thus, the Reed-Solomon code decoding device achieves an increase in speed due to the fact that the coefficients of the polynomial coefficients of the generalized checks based on the intermediate values of the coefficients of the erase locator polynomial and codeword symbols are computed in parallel with the calculation of the erase locator polynomial generated during the reception of the codeword.

In addition, when multiplying polynomials, n-k cycles are further saved.

The complexity of block 3 of calculating the polynomial of generalized checks grows in proportion to the first degree nk, and not to the square, as in the known device, so for large nk values the proposed block 3 structure is more economical than known. Another advantage can be considered the absence of a special synchronization scheme used in the known device for multiplying polynomials, since the synchronization is provided by the clock frequency of receiving the input symbols.

Claims (1)

Invention Formula "V A device for decoding Reed-Solomon codes containing an input: a unit whose inputs are device inputs, the first outputs of an input unit are connected to the corresponding inputs of a buffer accumulator whose outputs are connected to the first inputs of an adder unit, a key equation solving unit whose outputs are connected to the first the inputs of the correction block, the second outputs of the input block are connected to the inputs of the computing block of the erase locator polynomial, the outputs of which are connected to the second inputs of the correction block whose outputs connected to the second inputs of the block of adders, the outputs of which are the outputs of the device, the calculating block of the polynomial of generalized checks, consisting of n-k sections (n is the common to the constant are connected to the first and second inputs of the second adder, the outputs of which are connected to the second inputs of the first adder of this section of the characters of the input code 5th unit and to the first inputs of the first multiplier of the next section, the first inputs of the first multiplier of the first section and the second inputs of the third adders of all sections combined and connected to the bus of the logical unit, the second inputs of the fourth adder of the first section are connected to the bus of logical zero, the second inputs of the second multipliers of all sections and the second and the multiplier, in each section, the inputs of the third multipliers of all sections of the polynomial generalized Qi calculations are combined and checked, the second - the fourth are entered respectively to the first output adders, the first - the third multiplier of the input block and to the outputs of the block and Galois field generator of the computation of a locator polynomial, the error outputs of which are connected to the first 20 OK, the outputs of the second and fourth meters with the inputs of the third multiplier, the outputs of which are connected to the first va, k is the number of its information symbols), each of which contains a first adder connected in series, a register and a multiplier to a constant, a bus of a logical zero and a bus of a logical unit that corresponds to, in order to increase the speed of the device, he entered the floor generator Galois The mators of the last section are connected to the inputs of the key equation solving unit and the third inputs of the correction unit, the outputs of the generator of Galois field elements 25 are connected to the first inputs of the multiplier, the second inputs of which are connected to the corresponding second outputs of the input block, and the multiplier codes are connected to the second the inputs of the fourth adder, the outputs of which are connected to the first inputs of the third adder of this section and to the second inputs of the fourth adder of the subsequent section, the outputs of the first multiplier are connected to the first inputs of the first adder, the ejectors of the last section are connected to the inputs of the key equation solving unit and the third inputs of the block the coils, the outputs of the generator of elements 25 Galois fields are connected to the first inputs of the multiplier, the second inputs to which are connected to the corresponding second outputs of the input unit, alternately residents are connected to the second the moves of the third adder are connected to the 30 inputs of the first multipliers of all the first inputs of the second multiplier, the sections of the polynomial computing unit whose outputs and outputs of the multiplier generalized checks. - ck 13093176 to the constant are connected to the first and second inputs of the second adder, the outputs of which are connected to the second inputs of the first adder of the given third multipliers of all secs Qi, respectively, are combined and connected respectively to the first outputs of the input block and the outputs of the error locator polynomial calculator the outputs of the second and fourth about with the mind The mators of the last section are connected to the inputs of the key equation solving unit and the third inputs of the correction unit, the outputs of the generator of Galois field elements are connected to the first inputs of the multiplier, the second inputs of which are connected to the corresponding second outputs of the input unit, and the multiplier codes are connected to the second the inputs of the first sections of the block is calculated generalized checks.