JPH0936741A - Analog/digital converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct the deterioration in the accuracy due to offset of an analog/digital converting circuit with a simple configuration. SOLUTION: A difference between outputs of two A/D converters 2, 3 is obtained by a subtractor 4 and the result of subtraction is latched by a latch circuit 5 as an offset difference. The latched output is added to a conversion output by the A/D converter 3 to correct the offset.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital conversion circuit, and more particularly, to an analog signal as a common input.
The present invention relates to an analog-digital conversion circuit that includes two analog-digital converters (hereinafter, abbreviated as A / D converters) and alternately outputs converted outputs of these two converters to a common terminal.

[0002]

2. Description of the Related Art It is known that by operating A / D converters in parallel, an analog-digital conversion circuit capable of high-speed operation as a whole circuit can be constructed. This conventional analog-digital conversion circuit will be described with reference to FIG. As shown in the figure, the conventional analog-digital conversion circuit has an A / D converter (AD) connected in parallel.
C) 2 and 3, a signal input terminal 1 common to both converters, a selector circuit 7 for selectively sending the outputs of both converters, and an output terminal 8 for the A / D conversion result It is configured to include.

In such a configuration, A / D converters 2 and 3
The input signal A-IN is applied to each of the input terminals. Then, the A / D converters 2 and 3 are driven by the clocks a and b that are shifted from each other by a half cycle, and the output of each A / D is input to the selector 7. The selector 7 outputs the A / D conversion result AD-OUT to the terminal 8 every half cycle of the clocks a and b.

FIG. 5 shows an A-IN waveform of an input signal of an analog signal whose value changes with the lapse of time and a binary value of the A / D conversion result AD-OUT as an integer value (decimal). The waveforms, the drive clock a of the A / D converter 2 and the drive clock b of the A / D converter 3 are shown. Normally, the comparators and operational amplifiers that form the A / D converters 2 and 3 have a DC offset voltage. Therefore, the AD-OU shown in FIG.
As seen in T, the waveform shifts by the DC offset voltage every half cycle of the clock.

In Japanese Laid-Open Patent Publication No. 61-53829 (offset correction circuit for A / D converter), the output results of the first and second A / D converters are input to the memory,
After that, a method of correcting the offset voltage via the CPU is disclosed.

The A / D conversion circuit having the above configuration is usually called an interleave type.

[0007]

In the above-mentioned conventional analog-digital conversion circuit, as shown in FIG. 4, the waveform distortion occurs due to the difference in the DC offset of the A / D converters arranged in parallel. There was a drawback.

Further, the configuration described in the above-mentioned publication for correcting the offset has a drawback that a large-scale memory and a CPU are required.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and its object is an analog-to-digital conversion circuit capable of correcting the accuracy deterioration due to the offset without requiring a large-scale memory or the like. Is to provide.

[0010]

An analog-digital conversion circuit according to the present invention includes two analog-digital converters having an analog signal whose value changes with time as a common input, and conversion outputs of these two converters. Is an analog-digital conversion circuit that alternately outputs to a common terminal, and an offset holding unit that holds an offset difference between outputs of the two converters, and the converted output is corrected according to a holding output of the holding unit. A correction means is included.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.

The difference between the outputs of the two A / D converters is obtained by the subtractor, and the result of this subtraction is held in the latch circuit as the offset difference. The converted output of the A / D converter is corrected according to the held output. Preferably, the subtractor finds the difference between the outputs of the two A / D converters depending on the values of the analog signal at the same time.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of an analog-digital conversion circuit according to the present invention,
4 are denoted by the same reference numerals. In the figure, the analog-digital conversion circuit according to the present embodiment is
In the configuration of FIG. 4, the output of the A / D converter 2 and the A / D converter 3
Subtractor (SUB) 4 for obtaining the difference from the output of L, a latch circuit 5 that holds the result of this subtraction at the falling timing of control signal S, and the output held by this latch circuit 5 as the output of A / D converter 3. And an adder circuit (ADD) for adding to.

In such a configuration, the input signal A-IN input to the common input terminal 1 is A / D converters 2 and 3.
Is input to The A / D converter 2 is driven by the clock a and the A / D converter 3 is driven by the clock b, respectively, and the input signal A-IN
Are converted into digital signals respectively.

Both output signals of the A / D converters 2 and 3 are subtracted by the subtractor 4, and the output is input to the latch circuit 5. The input signal to the latch circuit 5 is the A / D converter 2
And the output offset difference of the A / D converter 3. This output offset difference is held in the latch circuit 5 at the timing when the control signal S switches from high level to low level.

The output of the A / D converter 2 is directly input to the selector 7. The output of the A / D converter 3 is input to the selector 7 after the offset signal held in the latch circuit 5 is added in the adder 6.

The selector 7 offset-corrects the value that is A / D converted by the A / D converter 2 and the value that is A / D converted by the A / D converter 3 every half cycle of the clocks a and b. The values and are output alternately.

FIG. 2 is a time chart showing the above operation.

In the figure, the same parts as in FIG. 5 are designated by the same reference numerals.

As shown in the figure, the input signals AI
The value of the N waveform changes with the passage of time. The output of the subtractor 4 is the difference between the outputs of the A / D converters 2 and 3, that is, the output offset difference, and this offset difference is
At the falling timing T of the control signal S, the latch circuit 5
Is held. As a result, the latch circuit 5 continues to output the offset difference.

This offset difference is input to the adder 5,
It is added to the output of the A / D converter 3. Therefore, the addition result of the adder 5 is offset-corrected. That is, in this circuit, the offset difference between the outputs of the two A / D converters is held, and the A / D conversion result is corrected according to the held output.

As a result, the A / D conversion result AD-OUT
As shown in the figure, the result is a highly accurate conversion result without distortion. Moreover, the conversion result with high accuracy is
It can be obtained with a simple structure as shown in FIG.

FIG. 3 shows an A / D according to the second embodiment of the present invention.
It is a block diagram which shows the structure of a conversion circuit.

In the figure, blocks, terminals and the like having the same functions as those in FIG. 1 showing the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In the above-described first embodiment, the A / D converters 2 and 3 are driven by different clocks a and b, respectively, during the period in which the offset signal is extracted, that is, the control signal S is at the high level. Therefore, the sampling points are shifted by half a cycle. Therefore, a difference may occur in the offset voltage. In particular, when the input signal changes abruptly, the voltage difference at the sampling point is large, which causes a large error in the offset voltage.

Therefore, in the present embodiment, the selector circuit 12
Is added, the clock a is selected as the drive clock of the A / D converter 2 in the selector circuit 12 while the control signal S is at the high level. As a result, the subtractor 4 obtains the difference between the outputs of both converters depending on the value of the input signal A-IN at the same time, and the error generated in the offset voltage can be eliminated.

The present invention can take the following aspects in connection with the description of the claims.

(4) The correction means includes an adder for adding the held output to only one of the converted outputs of the two converters. The analog according to any one of claims 1 to 3, Digital conversion circuit.

[0030]

As described above, the present invention achieves a conversion rate twice as high as the conversion speed of each A / D converter by correcting the offset voltage generated between the A / D converters operated in parallel. At the same time, it is possible to correct the deterioration of accuracy due to the offset voltage and realize a high-speed A / D conversion circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an analog-digital conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the analog-digital conversion circuit of FIG.

FIG. 3 is a block diagram showing a configuration of an analog-digital conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional analog-digital conversion circuit.

5 is a time chart showing the operation of the analog-digital conversion circuit of FIG.

[Explanation of symbols]

 2, 3 A / D conversion circuit 4 Subtractor 5 Latch circuit 6 Adder 7, 12 Selector

Claims (3)

[Claims] 1. An analog-to-digital conversion circuit which includes two analog-to-digital converters having an analog signal whose value changes according to the passage of time as a common input, and which outputs conversion outputs of these two converters alternately to a common terminal The analog-to-digital conversion includes: an offset holding unit that holds an offset difference between the outputs of the two converters; and a correction unit that corrects the converted output according to the held output of the holding unit. circuit. 2. The analog-digital device according to claim 1, wherein the offset holding means includes a subtracter for obtaining a difference between outputs of the two converters and a latch circuit for holding a result of the subtraction. Conversion circuit. 3. The analog-digital conversion circuit according to claim 2, wherein the subtractor obtains a difference between outputs of the two converters according to a value of the analog signal at the same time.