JPH0529939A - A/d converter - Google Patents

Abstract

PURPOSE:To attain low power consumption at a high speed by providing the adjustment mode to the converter in addition to the mode of A/D conversion, applying a same input signal to two A/D converters at the adjustment and converting the signal into a digital signal and detecting a difference between the conversion gains. CONSTITUTION:A clock distributer 20 outputs sampling command signals C1, C2 to sample-and-hold circuits 12,13 and similarly outputs same conversion command signals C3, C4 to A/D converters 14, 15. An adder 16 adds an offset correction signal to an output of the converter 15 and a multiplier 17 multiplies a gain correction signal with an output of the adder 16 and outputs the result. A subtractor 18 outputs an output difference between the converter 14 and the multiplier 17. A control circuit 19 receives an output of the subtractor 18 to adjust the correction signal. A level discrimination device 25 throws a switch 26 to the position of an integration device 21 when the output of a D/A converter 14 is less than a prescribed value R1 and throws the switch 26 to the position of an integration device 22 when the output of the D/A converter 14 is larger than the prescribed value R1. Outputs of the integration devices 21,22 are outputted to sample-and-hold circuits 23, 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-digital converter for converting an analog signal into a digital signal.

[0002]

2. Description of the Related Art In recent years, a system for converting an analog signal into a digital signal and realizing various kinds of signal processing by digital signal processing has been actively developed, and a system having a high sampling frequency has become available as a processing object is diversified. It has come to be requested. In order to meet this demand, an all-parallel type analog-digital conversion device has been developed.

An example of the above-mentioned conventional analog-digital conversion device will be described below with reference to the drawings.

FIG. 4 shows the structure of a conventional analog-digital converter. FIG. 5 is a diagram for explaining the operation. In FIG. 4, 1 is a buffer. Reference numeral 2 is a ladder resistance network, 3 is a series of comparators, 4 is a reference voltage source, and supplies specific reference voltages REf1 and REF2 to the ladder resistance 2. Reference numeral 5 is a decoder.

The operation of the analog-to-digital converter having the above structure will be described below.

First, the reference voltage generated by the reference voltage source 3
REF1 and REF2 are supplied to both ends of the ladder resistor 2. As shown in FIG. 5A, the ladder resistor 2 resistance-divides the reference voltages REF1 and REF2 at a predetermined division ratio and supplies the reference voltages REF1 and REF2 to the comparator (comparison voltage) inputs of the comparator row 3. An input signal is supplied to the other input of each comparator through the buffer 1. Thus, the comparison voltage of the comparator row 3 is the reference voltages REF1 and RE.
It is determined by the division ratio of F2 and ladder resistance 2, and each comparator outputs 1 when the input signal is larger than the comparison voltage as shown in (b) and 0 when it is smaller than the comparison voltage. The decoder 5 encodes the output of the comparator array 3 into a binary number and outputs it. The sampling clock signal that gives the sampling timing is used to latch the output in the decoder 4, and is supplied as the clock when a synchronous comparator is used in the comparator array 3. Here, the number of comparators in the comparator array 3 is 128 when the quantization resolution of the analog-digital converter is 7 bits, and 2 when it is 8 bits.
It is 56. The above-mentioned configuration is called an all-parallel type analog-digital converter, and is approximately 250 m at a sampling frequency of 20 MHz by integration using a complementary metal oxide semiconductor (hereinafter referred to as CMOS) process.
A low power consumption of about W has been realized.

[0007]

However, it is difficult to realize sampling at a higher frequency with the conventional analog-to-digital converter configuration as described above, and in the bipolar process capable of coping with high speed. There is a problem that the power consumption becomes higher than that in the CMOS process.

In view of the above problems of the conventional analog-digital converter, it is an object of the present invention to provide a high-speed analog-digital converter with relatively low power consumption.

[0009]

The analog-to-digital converter of the present invention comprises sample-hold means for sample-holding an input signal in accordance with a sampling instruction signal,
First and second analogs for converting the output of the sample hold means into a digital signal according to a conversion instruction signal.
Digital converting means, adding means for adding and outputting an offset correction signal to the output of the first analog-digital converting means, multiplying means for multiplying the output of the adding means by a gain correction signal and outputting the multiplied output, 2 subtraction means for taking the difference between the output of the analog-digital conversion means and the output of the multiplication means, and the output of the first or second analog-digital conversion means and the subtraction means during the adjusting operation. The offset correction signal is adjusted when the output value of the analog-to-digital conversion means is in the preset first specific range with the output as an input, and the gain correction is similarly performed when it is in the second specific range. Control means for adjusting and outputting signals, and holding and outputting these correction signals during normal operation, and the sampling instruction signal and the sampling instruction signal according to the sampling clock signal. The conversion instruction signal is output to shift the phase of the conversion instruction signal to the first analog-digital conversion means from the phase of the second analog-digital conversion means by 180 degrees during normal operation, and eliminate the phase difference during adjustment operation. It is an analog-to-digital conversion device having a clock distribution means for outputting.

[0010]

According to the present invention, by the above-mentioned structure, the adjustment mode is provided in addition to the normal analog-digital conversion operation,
At the time of the adjusting operation, the same input signal is applied to the two analog-digital conversion means, digital conversion is performed at the same sampling timing, and the difference between the conversion gains is detected, whereby the offset correction and gain of the output of one analog-digital conversion means The correction is performed digitally to correct the variation in the conversion gain characteristic of each analog-digital conversion means. In this way, two analog-digital conversion means having equivalent characteristics are realized, and by sequentially using these in normal operation, an analog-digital conversion device capable of high-speed sampling is realized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An analog-digital converter according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic configuration of an analog-digital conversion apparatus according to an embodiment of the present invention. 2 is a signal waveform diagram in the normal operation of FIG. 1, and FIG. 3 is a signal waveform diagram in the adjustment operation. In FIG. 1, 11 is a buffer,
Reference numerals 12 and 13 are sample and hold, 14 and 15 are analog-digital converters, 16 is an adder, 17 is a multiplier, 18 is a subtractor, 19 is a control circuit, and 20 is a clock distributor. Reference numerals 21 and 22 are integrators, 23 and 24 are sample and hold, 25 is a level determiner, and 26 is a switch.
4, the level determiner 25, and the switch 26 form a control circuit 19.

With respect to the analog-digital converter having the above-mentioned structure, its concrete structure and operation will be described below with reference to FIGS. 1, 2 and 3.

First, FIG. 2 shows a signal waveform at the time of normal operation in FIG. 1, in which the input signal (a) supplied through the buffer 11 is supplied to the sample-holds 12 and 13 respectively (c) and (). sampling instruction signal C shown in e)
The sample is held at 1 and C2. Therefore, the outputs of the sample and hold 12 and 13 are as shown in (d) and (f). The analog-digital converters 14 and 15 operate at the timings of the conversion instruction signals C3 and C4 shown in (e) and (c) and convert the outputs of the sample and hold 12 and 13 into digital signals and output them. At this time, the final analog-digital conversion output is, for example, as shown in (g), the output of the analog-digital converter 14 and the output of the multiplier 17 are arranged so as to be time-multiplexed. The clock distributor 20 has a sampling clock signal as an input, a frequency divider that divides the sampling clock signal by two, and a gate function that switches the phase of the frequency-divided output, and the sampling instruction described above according to the adjustment operation and the normal operation. The signals C1 and C2 and the conversion instruction signals C3 and C4 are generated and output. The analog-digital converters 14 and 15 are the same as those in the conventional example, and operate with a common reference voltage source. The output signals of these analog-digital converters are so-called offset binary codes, and the minimum value is 0 and the maximum value is a positive specific value determined by the bit resolution.

During the adjusting operation, the clock distributor 20 moves to the sample and hold 12 and 13 (c) as shown in FIG.
The same sampling instruction signals C1 and C2 shown in (1) are output, and similarly, the same conversion instruction signals C3 and C4 are output to the analog-digital converters 14 and 15 as shown in (e). Therefore, the outputs of the analog-digital converters 14 and 15 are those obtained by digitally converting the same input signal at the same timing as shown in (f), but the results of both are slightly due to variations in the conversion gain characteristics. Difference occurs. The adder 16 adds the offset correction signal to the output of the analog-digital converter 15 and outputs it, and the multiplier 17
Outputs the output of the adder 16 multiplied by the gain correction signal. The subtractor 18 takes the difference between the output of the analog-digital converter 14 and the output of the multiplier 17, and outputs it. In this case, the subtractor 18
The output represents the difference between the offsets of the conversion gain characteristics of the outputs of the analog-to-digital converters 14 and 15 when the input signal level is low, and when the input signal level is high and the offset is well corrected. Indicates the difference in conversion gain. The control circuit 19 includes a level determiner 25, integrators 21 and 22, and sample and hold 23 and 24, and adjusts the offset correction signal and the gain correction signal by using the output of the subtracter 18 as an input. During this adjustment operation, as shown in (g), the level determiner 25 sets the switch 26 to the integrator 21 connection mode as the mode 2 when the output of the analog-digital converter 14 is smaller than the first specific value R1. 2 specific value R2
It is connected to integrator 22 as mode 3 when larger. In other cases, the switch 26 is in the released state as the mode 1. The integrators 21 and 22 integrate the output of the switch 26 and output it to the sample and hold 23 and 24.
The sample hold 23 outputs the output of the integrator 21 as the offset correction signal, and similarly, the sample hold 24 outputs the output of the integrator 22 as the gain correction signal. When the adjustment operation is changed to the normal operation, the above-mentioned offset correction signal and gain correction signal are held and output by the sample and hold 23 and 24, respectively.

As described above, when the digitally converted input signal is smaller than the specific first value R1, the offset correction signal is adjusted so that the output of the adder 18 is converged to around 0, and the specific second value is obtained. When the value is larger than the value R2, the gain correction signal is adjusted so that the output of the subtractor 18 converges near 0. For example, when the digital conversion output is small,
If the offset correction signal is 0 and the output of the analog-digital converter 15 is smaller than the output of the analog-digital converter 14, the output of the subtractor 18 becomes a positive value, and the output of the subtractor 18 is integrated by the integrator 21 to generate the offset. As the correction signal increases, as a result, the output of the subtracter 18 is almost 0.
To work. At this time, since the gain correction instruction signal value is approximately 1 and the output of the analog-digital converter 15 is close to 0, the effect of the gain correction signal on this offset correction signal adjustment is small and can be ignored.
The same applies to the adjustment of the gain correction signal.

As described above, according to the present embodiment, the adder for correcting the offset of the output of one analog-digital converter, the multiplier for correcting the gain, the output of the other analog-digital converter and the multiplier. A subtracter that outputs the difference in output, a control circuit that adjusts the offset correction amount and the gain correction amount, and the conversion instruction signal of the analog-digital converter are the same during the adjustment, and the phase of the conversion instruction signal is 180 in normal operation. By providing the clock distributor that causes the shift, it is possible to digitally correct the variation in the conversion gain characteristics of the two analog-digital converters.

In this embodiment, the sample-hold is provided for each of the two analog-digital converters. However, when the operating frequency of the analog-digital converter is relatively high, the number of sample-holds is reduced to one. It is also possible to operate with a sampling instruction signal of double the frequency and supply this to two analog-digital converters, in which case the circuit scale can be reduced.

In the above example, the output of the analog-digital converter is an offset binary. However, this may be a commonly used two's complement expression. In this case, the two's complement is offset binary. As described above, the specific offset may be added to correct the series of conversion gains, and at the same time, the specific offset may be subtracted and output as an analog-digital conversion output.

[0020]

As described above, according to the present invention, the parallel operation of the analog-digital conversion means realizes a substantially high sampling frequency even when the sampling frequency per unit is low, and the conversion of the analog-digital conversion means is realized. It has an advantage that the deterioration of the quantization resolution due to the characteristic variation can be compensated digitally.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an analog-digital conversion device according to an embodiment of the present invention.

FIG. 2 is a first signal waveform diagram for explaining the operation in the embodiment of FIG.

FIG. 3 is a second signal waveform diagram for explaining the operation in the example.

FIG. 4 is a configuration diagram of a conventional example.

FIG. 5 is a signal waveform diagram for explaining the operation of the conventional example.

[Explanation of symbols]

1, 11 buffer 2 ladder resistance 3 comparator 4 Reference voltage source 5 decoder 12, 13, 23, 24 Sample and hold 14, 15 Analog-digital converter 16 adder 17 Multiplier 18 Subtractor 19 Control circuit 20 clock distributor 21, 22 integrator 25 level judge 26 switch

Claims (2)

[Claims] 1. A sample hold means for sampling and holding an input signal in accordance with a sampling instruction signal, first and second analog-digital conversion means for converting an output of the sample hold means into a digital signal in accordance with a conversion instruction signal, and An adding means for adding an offset correction signal to the output of the first analog-digital converting means and outputting the same, a multiplying means for multiplying the output of the adding means by a gain correction signal, and outputting the second analog-digital converting means. A subtracting means for taking the difference between the output of the means and the output of the multiplying means, and outputting the difference, and an analog-input using the output of the first or second analog-digital converting means and the output of the subtracting means during the adjusting operation. The offset correction is performed when the value of the output of the digital converting means is within a preset first specific range. The signal is adjusted, the gain correction signal is adjusted and output when the signal is in the second specific range, and the correction signal is held and output during normal operation, and the sampling instruction signal is output according to the sampling clock signal. And outputting the conversion instructing signal to shift the phase of the conversion instructing signal to the first analog-digital converting means and the second analog-digital converting means by 180 degrees in the normal operation, and this phase difference in the adjusting operation. An analog-to-digital conversion device comprising: a clock distribution means for eliminating and outputting. 2. A first and a second sample-and-hold for sampling and holding the switch output, each output being output to the first and second analog-to-digital conversion means, respectively. The described analog-to-digital converter.