SU1564630A1 - Device for debugging multimodule central computer - Google Patents

Abstract

The invention relates to computing and can be used for debugging and operational control of complex digital devices for various purposes. The purpose of the invention is to reduce the time for debugging and monitoring, as well as to expand the functionality for monitoring digital computers with a multi-module structure. The device for debugging a multi-module digital computer contains a debugging digital computer, a firmware control block, a register block, a register of a debugging digital mode card, an interrupt block, interface modules with functional modules, a module for simulating a module. The device provides operation in the following modes: writing information to functional modules, reading information from functional modules of a debugging digital computer, simulating the operation of a digital computer. The order of switching on of one or another operation mode is determined by the control and debugging program of the digital computer, or by manual actions of the operator on the keyboard of the display of the same device. Building a block on the basis of microprogrammability allows implementing a flexible algorithm for controlling the system, and the use of a PLA in blocks of interrupts and module simulation allows one to significantly increase the efficiency of monitoring and debugging. 7 il.

Description

The device (Fig. 1) contains a debugging digital computer 1, microprogram control unit 2, a register block 3, a register of 4 modes, a bitwise comparison block 5, blocks 6.1 ... 6.N interface with the functional modules of the debugged digital computer, imitation block 7 module, information output 8, information input 9, group

10 outputs control floor group

11 control field outputs, interrupt input 12, output 7 of block 7, output group 4, control field output group 15, output 16, synchronization output 17, informational input-output 18 and 19, control output group 20, output group 21, 22 and 23 control field, output 2 & bpkirovka, group of 25 exits, group of 2.6 exits,

Block 6 is associated with functional modules and contains a register 27, a bidirectional bus driver 28, item 29, memory node 30.

Block 7 contains the receiving register 31, transmitting the register 32, the register

33 settings, memory node 34, bus driver 35, element 36.

Unit 2 contains a node 37 for selecting the next micro-command, a node 38 for storing micro-commands, register 30 for micro-commands, pulse generator 40, element 41, multiplexer 42.

Block 3 contains a read register 43 and a write register 44.

Block 5 contains a one-bit comparison node, consisting of series-connected elements ЗК-2И 45, with the element NE 46 connected to it, the elements NOT 47 and OR 48 and the trigger 49.

A device for debugging a multi-module digital computer provides operation in the following modes: recording information into functional devices of a debugged digital computer (in Fig. 1, not shown, in Fig. 5 - block symbols 1-12); reading information from functional devices of the debugging digital computer (FIG.

block characters 1-6, 13-17); imitation of work of the debugged digital computer (Figures 5 and 6, block symbols 1-6, 18-30).

The order of switching on of one or another operation mode is determined by the debugging program of the debugging digital computer or by the operator’s manual actions on the display keyboard of the same device.

In simulation mode, the device allows you to tune to

ten

Jq and 4q

d $,

646304

This physical interface of an external digital computer that defines the input and output communication lines of buses 18. The simulated debugging digital computer simulation program can be triggered with a certain periodicity or by interrupt signals from block 5 of a bit comparison.

The device 1 operates in the modes of recording and reading information (information buses 8, 9, control buses II, 12).

In the recording mode, for transmitting each information word, the DVR 1 generates test actions and analyzes the reactions transmits the control and then the information word (Fig. 7, block symbols 31-39).

In the read mode, the digital computer 1 transmits a control word and then reads the information word (Fig. 7, block symbols 31-36, 40).

A device for debugging a multi-module digital computer operates as follows.

In the initial state from the output of the node 38 and, respectively, from the output of the register 39, signal 15 is transmitted through line 10 to

20

25

50

55

cash Receiver readiness (D).

The digital computer 1 sets up a control word on bus 8 and transmits a transmission synchronization signal at output 11, which through multiplexer 42 enters the input of node 37, as a result of which the next differential signal from the generator of 40 pulses at the output of node 37 is generated and transmitted to node 38 A new address at which another microcommand is selected (Fig. 5, block sync 1-6). At the output of node 38, and a signal from the pulse generator 40 and the output of register 39 generate a signal that synchronizes the control word to register 4.

The control word contains two significant fields. The first field contains the read (write) flag and the binary code of the specified register of the debugging digital computer or the register code 31, 32 and 33. The second field contains the initial address code of the corresponding microcommand of block 2.

Consider the case when the control word is set to the write mode in one of the registers of the debugged digital computer.

An address code with a write attribute is transmitted from register 4 to output 14 of block 6 and 7 to the inputs of nodes 30 and 34

memory made on software logic matrices. In this case, the register of the debugged computer is specified, which is in the ith function module. Accordingly, the node 30 of the memory of the 1st block 6 is configured on the corresponding group of address codes defining the registers of this function module. Next, the firmware is started, the starting address of which is loaded from the half of the register of 4 modes.

Further, in accordance with the firmware, the output of the register 39 is generated and transmitted over the 10-bus bus Ready receiver Gpr, at the same time multiplexer 42 is configured to receive the synchronization signal (figure 5, block symbols 7-12). When the firmware is executed, the node 37 reads each subsequent address from the register 39, which in turn receives this address as part of the next microcommand from the node 38. DVM 1 sets an information word on output 8 and transmits a synchronization signal, which selects the new microcommand node 38 and is transmitted to the inputs of register 39.

The composition of this microcommand contains a write bit to register 44, as a result of which the information word is written to the specified register. A register address code belonging to the region of interaction addresses with i block 6 and previously recorded in register 4 is transmitted via bus 14 to inputs of memory nodes 30 and 34. In accordance with the firmware, block 2 k transmits via bus 15 to the inputs of memory nodes 30 and 34 signals that record the information word in a given register of the debugged digital computer. In the course of this operation, at the output of the memory node 30 of the 1st block 6, a signal is generated that switches the register 27 to the sequential shift mode, then the information from the register 44 is sequentially overwritten into the register 27 of the same block 6.

Serial transmission is performed as follows.

The input element And 41 of block 2 is supplied with a potential shift resolution signal, to another input — clock pulses from generator 40. At the output of this element, shift pulses are generated, which enter the shift circuit of register 44 switched

0

five

0

five

0

five

0

five

0

five

in the sequential shift mode signal from the register 39 of the block 2. In addition, the shift signals are received through the bus 17 shift in the shift circuit of the registers 27.

The information is supplied with a single-phase code from the output of register 44 via bus 16 to the inputs of registers 27, while recording is performed in that block 6, which is specified by the range of address codes from register 4. Thus, information is recorded in register 27 of block 6. Upon completion of the sequential transmission of information the firmware generates a signal, which in turn causes the appearance of a signal at the output of the node 30 switching the bi-directional bus driver 28, and the transmission of information from the output of the register 27 to the information slots 191 (input-output). Thus, the information word is transmitted over these buses to the function module of the debugged digital computer, in which there are bi-directional buses connected to the information inputs of the registers. The outputs of the module registers through the switches are connected to the same bus. Then, from another output of the same memory node, a write signal is transmitted to the buses 20. This signal is fed to the write synchronization input of the specified register. The write circuit from the control unit in the function module of the digital computer is combined with a signal of a similar purpose, coming from the 2C bus by the OR installation. Thus, information is recorded from register 27 to the specified register of the function module of the debugged digital computer.

In read mode, the control word is also written to register 4. In node 37, the starting address of the other firmware is loaded. The address code is also transmitted to the inputs of the nodes 30, 34. Next, the firmware generates and transmits a signal through the buses 15 that causes the output of the node 30 to form a polling signal for a given register of a digital computer function device, which is transmitted over buses 20 and causes the connection of a given register to input-output 19 (figure 5, block symbols 13-17). The bi-directional bus driver 28 in its initial state passes the signals of buses 19 to the input of register 27. Then a write signal to register 27 is generated by a signal from buses 15 and information about

When the specified register is set, a parallel code is written into register 27. Next, in accordance with the firmware, register 27 is switched to the sequential shift mode, the enabling signal level to the input of the And 29 element is set, the register 43 of the block 3 is simultaneously set to the sequential shift mode, and register 27 through the element 29, the bus 13 into the register 43 of the block 3. The shift of the registers is carried out by the shift signals generated at the output of the element 41 of the block 2 and transmitted to the block 3 via the bus e 17 blocks 6. After a transmission word in the register 43 and the outputs of respectively the inlet 9 exhibited an information word on a state of a predetermined register debugged DCM.

The firmware generates a readiness signal for the information transfer Gg, d, which is transmitted on output 10 to digital computer 1. The latter organizes the reading of information from input 9, after which it sends an acknowledgment signal II p on output 11, then analyzes and continues the specified program.

Consider the operation of the device in the implementation of the imitation mode of external devices.

At the beginning of the work, the block 7 is set up to simulate this type of computing device, and the communication lines in the bus 18 are distributed to the input and output. For this, PC 1 transmits a control word with an address field in which the operation code for memory block 34 of block 7 is set. Then, an information word is transmitted that through output 8, register 44, output 16 is written to register 33 of block 7 (Fig.6 , block signals 18-21). The shift of the register 33 is carried out on the bus 16, the permission to operate in the sequential shift mode is generated at the output of the node 34 under the action of a signal from the bus 15 specified by block 2.

Upon completion of writing to register 33, block 7 is considered tuned to simulate a given type of slave. This is determined by the presence of single and zero signals at individual bits of this register. Each register bit 33 is connected to a control input with

five

0

five

0

five

0

five

0

five

of the corresponding element with three states, part of the bus driver 35. The number of these elements in the driver 35 corresponds to the size of the registers 32 and 33, and the corresponding outputs of the register bits 32 are connected to the information inputs of these elements. ), which have a permitting signal level at the control input, connect the output of the corresponding register bit to the bus 18 and designate the output lines, and elements (35) that have a forbidding signal level at the same input remain at the output in a high impedance state. Since the bus 18 is connected to the information inputs of the register 31, the bits having no input on the inputs; different state, refer to the input lines.

Signals are issued over bus 18 in a manner similar to that described. In this case, instead of register 33, it activates the register 32. Signals from the output of register 32 are transmitted via elements (35) to bus 18 (Fig. 6, block symbols 22-26) about. Reading information from bus 18 is performed on the control word, while information in parallel code is written to register 31, then transmitted by a serial code through AND 36 on output 13 to register 43, from which I is read into device I (FIG. 6, block symbols 27-30). The registers involved in the sequential transmission of information are controlled by blocks 2 and 7.

Consider the operation of the device with the formation of the signal Interrupt.

In register 31 of block 7, a constant is written from the digital computer 1 setting the parameters of the expected input signal. Writing to the register is done in the same way as described. Register 31 is connected at the outputs of its bit size to the input of node 5 of bitwise comparison of the block, where each of the n-1 register bits is connected to the input of the corresponding element ZI-2ILI 45, and the n-th bit (sign) - to the element NO 46 (n is the total number of register bits 3).

Bus 18 is connected to the inputs of the elements ZI-2ILI 45 and through the elements NOT 47 to the other inputs of the elements ZI 2ILI 45 (FIG. 4), i.e. in the absence of a signal with the specified parameters at the outputs of all

ZI-2ILI 45 elements and, accordingly, at the output of the OR 48 element, there are zero level signals. When a signal with specified parameters (a communication line is specified by a single level signal at one of the bits of register 31) appears, a single level signal appears at the output of the corresponding ZI-2IL 45 element, which through the OR 48 element turns on the trigger 49. the trigger output signal is transmitted to device 1, which causes the simulation program to turn on (FIG. 7, block symbols 31-41). The setup input to the initial state of the trigger 49 is controlled from block 20

Thus, the proposed device allows debugging and monitoring of multi-module digital computers, while blocks 6 and 7 can be placed at a considerable distance both from each other and from other blocks and devices of the system. This quality is achieved due to the same organization of interaction with each of these units using the same set of tires 13-17. The number of communication lines in the channel formed by tires 13-17 is insignificant due to the use of sequential information transmissions.

Claims (1)

Invention Formula A device for debugging a multi-module digital computer containing a microprogram control unit, a bitwise comparison unit, a register block, a mode register, the first input of the logic condition of the microprogram control unit connected to the input of the device for connecting to the control bus of the debugging digital computer, the first group of output control field of the microprogram control unit connected to the input of the device to connect to the address bus of the debugging digital computer, the second and third group of outputs of the control field of the microprogram unit pack ION coupled to the first and second groups of information inputs of registers block, a first output field sync blezha firmware control input connected to the synchronization register block, the fourth block group microprogram control outputs coupled to a group of information inputs PE10 15 25 so 20 35 ," five 0 five the mode hystera — the first group of outputs of which is connected to the second group of inputs of the logic condition of the microprogram control unit; the second group of information inputs of the mode register is connected to the inputs of the device for connection to the information debugging digital computer and to the third group of inspectors of the block of registers, the group of outputs of which is connected to the input of the device for connecting to the information bus of the debugging digital computer, the output of the device for connecting to the interrupt input of the debugging U3M is connected to the output of the block bit comparison, the blocking input of which is connected to the second output of the synchronization field of the firmware control block, is due to the fact that, with the speed reduction circuit of the CMV of the modular structure, a modulation unit N, interface blocks with functional modules of the debugged digital computer (where N is the number of modules in the debugged digital computer), the module of the module simulation contains the receiving register, the transmitting register, the setting register, the And element, the bus driver, the memory node, and each i-th block function couplings The main modules (i 1 ... N) contain a register, a bidirectional bus driver, an element And a memory node, the output group of the receiving register of the module simulation module is connected to the first group of information inputs of the bit comparison block, the second group of information inputs which is a group of device inputs for connecting with a group of information I / O of a debugging digital computer, with the first group of information inputs of the receive register of the modulating module i: with the group of outputs of the bus driver of the block imitating Module data, address and information inputs of the modular driver of the module simulation module are connected respectively to the outputs of the tuning register and the transmitting register of the module simulation module, the write-read inputs of the transmitting register, the tuning register and the receiving register of the module of the simulation module are connected to the output of the register block, and with inputs for reading and reading of registers N of interfacing blocks with functional modules The digital computer, the input of the record register of the module simulation module is connected to the first output of the synchronization field of the firmware control block and to the register write read inputs of the N interface blocks with the functional modules of the debugging digital computer, the first group of address inputs of the module module simulation block is connected to the second group the outputs of the register of modes and with the first group of outputs of the region of modes and with the first groups of address inputs of the nodes of the memory of the interfacing blocks with the functional modules of the debugged digital computer, the second group of address the inputs of the module memory node of the module are connected to the fifth group of outputs of the control field of the firmware control unit and the second groups of address inputs of the memory nodes N of the interface blocks with the functional modules of the debugging digital computer, in the module imitation module the second group of information inputs of the receiving module - the gistra is connected to the first group of outlets of the memory node, the second and third groups of the outputs of the memory node are connected to the groups of information inputs of the transmitting register and the tuning register, respectively, the output of the receiving and returning istra connected to the first building element, and output from the memory uzl 0 five dinene with the second input of the element I, the output of which is connected to the outputs of the elements AND N interface blocks with the functional modules of the debugged digital computer and connected to the input of the logic level of the register block, in the i-th interface block of the functional modules of the debugging digital computer the group of outputs of the register is connected with the group of information inputs of a bidirectional bus driver, the group of information inputs of the outputs of which is a group of information inputs of the outputs of the device for connecting to the i-th function module, debugging The digital computer, a group of outputs of a bidirectional bus driver, is connected to a group of information inputs of the register, the enable input of which is connected to the first output of the memory node, the second output of which is connected to the control input of a bi-directional bus driver, the group of outputs of the memory node is a group of outputs of the device control groups of inputs of the corresponding functional module of the debugging digital computer, the third output of the memory node is connected to the first input of the And element, the second input of which is connected to the output home register. t 24 four- i 40 I 41 , 17F15 2 1564630 V0 21 ъс 23 9 eight 21 44 22 k 13 17 sixteen Fig.Z (3 Cjed JLILIIJL Gg - “- Shyu i. KOnpt Ba2 W g №MXQti F & 5 SHShSchtst No. W - -Rgg7 / L. fl / tfr T Sdbi №7i-4 s43 L L / "WrJ .//-Ж f-ffjt. § r-tOISSh8 r-4fSdbig Sdbig Pr31- PrgZ g- & ISSh8- Pr & 4 Gpd Rg43-Sh9 -25. Shift Pr44- Prg32 Pr32 + Sh18 FIG. 6 I / Ш1 G START sЈ -. r-, shdotus 35 Thebes. 7 Editor M.Kelemes Compiled by A.Sirotska Tehred M. Khodanich Proofreader O. Kravtsova Order 1161 Circulation 567 All-Union Scientific Research Institute of State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 4/5, Moscow, Zh-35, Raushsk nab. 113035 -J8- G prog. I imitation ® Subscription