SU1261127A1 - Telegraph code transmitter - Google Patents

Abstract

The invention relates to a communication technique. The range of generated code combinations is expanded. The sensor contains a signal input unit 1, a starting signal shaper 2, a multiplexer 3, a switch (K) 4, a command setting block (BEECH) 5, two matching blocks 6 and 9, an address block (AB) 7, a prohibition element 8, an operational storage unit 10 and a shaper of code 11. The goal is achieved by introducing K 4 AB 7, a coincidence block 9 of multiplexer 3, which converts parallel code into serial, and BEECH 5, which performs a full cycle of commands when reading and writing sign code digits for the selected column. The difference of the sensor is also the performance of K 4, BEEC 5 and AB 7, illustrations of examples of their implementation are given. 3 hp f-ly, 4 ill. about S O) ND KJ

Description

one

The invention relates to communication technology and can be used to build telegraphic code sensors, in particular Morse code sensors.

The purpose of the invention is to expand the range of generated code combinations.

Fig. 1 shows the structural electrical circuit of the proposed sensorJ in Fig. 2 — switch, embodiment; in fig. 3- command installation block, an embodiment; in fig. 4 — address block, embodiment.

The telegraph code sensor contains (Fig. 1) signal input unit 1, driver 2 trigger signals, multiplexer 3, switch 4, command setting block 5, first block 6 matches, address block 7, prohibition element 8, second block 9 matches, operative storing block 10, the driver 11 code. The switch 4 contains (Fig. 2) two blocks 12 and 13 coincidence, two delay elements 14 and 15, and a collecting block 16. The command setting block 5 (Fig. 3) contains three collecting elements 17-19, a generator 20 and a distributor 21. Address block 7 contains (FIG. 4) three counters 22-24, a coincidence element 25, and a multiplexer 26.

Sensor telegraph code works as follows.

The signal input unit 1 at the first output (Fig. 1) generates a recording start signal, which is fed to the third input of the recording start of the driver 2 trigger signals. At the same time, on the other outputs of the signal input unit 1, a binary intermediate code appears in parallel form, which corresponds to the entered character. This code goes to the signal inputs of multiplexer 3 (parallel code-to-serial converter) and is fixed on it during the whole recording time. The recording time is determined by the driver 2 trigger signals. At the first output of the driver 2 trigger signals, a signal appears. Setting the record that is held on it for the time required to write the code from signal input unit 1 to the operational storage unit 10. Signal set record

12611272

From the second output of the driver 2, the trigger signals are fed in parallel to the first input of the switch 4, the matching block 12, the fourth writing control input 5 of the address block 7 (counter 22) and the second writing input of the command setting block 5, the collecting element 17.

ten

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20

In the initial state, the first group of outputs of the address block 7 (counter 22) contains the code of the address of the record of the first digit of the row (Fig. 4 is installed along the reset circuit at the moment the sensor is turned on and arriving in parallel to the address input of the random access memory block (RAM) 10 and to the control inputs of multiplexer 3. A multiplexer 3 that converts a parallel code into

thirty

sequential, in this case, only the first bit of the parallel code, which enters its inputs from block 1, passes to its output

25 input signals. At the same time, the command setting unit 5 (FIG. 3) generates at its third output, at the output of the collecting element 19, a Record command signal, and at the second output, at the output of the collecting element 18, a Select chip signal. At the moment of forming the command of the chip select command, the first element of the parallel code is recorded.

35 characters in RAM 10 at the specified address, i.e. in the first cell of the first row of the first column.

In the second group of outputs of the address block 7, the output of the multiplexer 26 contains the code for writing the address of the first column. This code on the second group of outputs of the address block 7 is kept for the entire recording time of 5 s of the first character entered in the RAM 10 in the field of the first line. After recording the first digit of the character code in the RAM 10, a signal is generated at the first output of the command setting unit 5, which

50 is fed to the installation sixth input of the address block 7 (the clock input of the counter 22). This signal at the outputs of address block 7 contains a new address code for the second line. This code ensures that the second character code passes through multiplexer 3 in RAM 10 in the same manner as indicated. On the information

In the initial state, the first group of outputs of the address block 7 (counter 22) contains the code of the address of the record of the first digit of the row (Fig. 4 is installed along the reset circuit at the moment the sensor is turned on and arriving in parallel to the address input of the random access memory block (RAM) 10 and to the control inputs of multiplexer 3. A multiplexer 3 that converts a parallel code into

sequential, in this case, only the first bit of the parallel code, which enters its inputs from block 1, passes to its output

input signals. At the same time, the command setting unit 5 (FIG. 3) generates at its third output, at the output of the collecting element 19, a Record command signal, and at the second output, at the output of the collecting element 18, a Select chip signal. At the moment of forming the command of the chip select command, the first element of the parallel code is recorded.

mark in RAM 10 at the specified address, i.e. in the first cell of the first row of the first column.

In the second group of outputs of the address block 7, at the output of multiplexer 26, there is a code for writing the address of the first column. This code on the second group of outputs of the address block 7 is kept for the entire time of the recording of the first character entered into the RAM 10 in the field of the first line. After recording the first digit of the character code in the RAM 10, a signal is generated at the first output of the command setting unit 5, which

arrives at the installation sixth input of the address block 7 (clock input of the counter 22). This signal at the outputs of address block 7 contains a new address code for the second line. This code ensures that the second character code passes through multiplexer 3 in RAM 10 in the same manner as indicated. On the information

the input of the RAM 10 elements of the character code are received through the element 8 of the prohibition. The address code of the entry of the selected column remains unchanged, and block 5 of the installation of commands, as indicated, fulfills the full cycle of commands specified by the generator 20 (Fig. 3) for recording the second digit of the character code. This process continues until all the lower case bits of the character code for the selected record column are written. After recording each digit of the character code, the counter 22 of the address unit 7 and the distributor 21 of the command setting unit 5 are reset to the third output of the switch 4 to the output of the collecting unit 16 (Fig. 2). Upon completion of recording all the code bits of the first character entered in the address block 7, the counter 23 is set to the signal from the first output of the switch 4 from the output of the delay element 14 in which the address of the second record column is set to the second group of outputs of the address block 7. The same signal restores the starting circuit of the recording of the generator 2 of block 1.

The signal from the third output of the switch 4 corresponds to the setting of the address (n + 1) of the line of the address block 7, i.e. complete end of the entry of the entered code of the mark. As a result of setting the address (n + 1) of the line at the ninth output of address block 7, a signal appears that goes to the third input of switch 4. This signal, having passed blocks 12 and 13 of coincidence, two delay elements 14 and 15 and the collecting unit 16 from its first output of switch 4 sets a new column address of the record (in this case, the second one) and supplies the signal from its third output and the initial state to the counter 22 of the addressing unit 7 and thus prepares the RAM 10 for the first bit code of the new mark. Upon receipt of the second character code from input unit 1, the indicated process of recording a new line of code repeats. At the time of recording, the signals from the output of the RAM unit 10 are missing since the second match unit 9 is locked. This process can last until the RAM 10 is completely filled. The shaper 11 of the code in the meantime generates the sign of the code entered on the hepBOM output.

The process of deriving the signs from RAM 1 is performed as follows. After the formation of the previous character has been completed, a read start signal appears at the output of the sensor from the second output of the former 11 and is fed to the fourth input of the former 2 trigger signals. In the case of simultaneous arrival of the signals Start recording and Start reading, the driver 2 start signals memorizes both of these signals and ensures the priority of the signal Start reading to avoid disturbing the interval between the characters that the driver 11 code

Signal Setting the readout from the second output of the driver 2 of the trigger signals in parallel to the second input of the switch 4, the fifth input of the address block 7, the third input of the command setting block 5, the second inputs of the first and second blocks 6 and 9 match and the prohibition element 8.

In the initial state, the second group of outputs of the address block 7 contains the read address code of the first line of the previously written first character. This code of the address of the first line of the first character, previously recorded in RAM 10, arrives in parallel to its address input of the lines. The output of multiplexer 3 is thereby blocked by prohibition element-8. At the same time, the command setting unit 5 generates a read command at its third output, and a chip select command signal at the second output, the chip select command provides the moment when information is read from the memory cell at the specified address. In the second group of outputs of the address block 7 there is a code for reading the addresses of the first column. This code at the output of the address block 7 is kept for the entire time to read the code of the previously recorded first character.

So, in the initial readout stage, a readable signal appears at the output of the RAM 10, corresponding to the first bit of the first read line. Code signals from the output of RAM 10, in accordance

With the order of reading the code bits through the second block 9, the matches are successively transmitted to the code generator 11. The input of characters to the code generator 11 is synchronized with the signals from the fourth output of the instruction setting unit 5 via the first matching unit 6. After reading the first digit of the character code from RAM 10, a signal is generated at the first output of block 5, which is fed to the setup (sixth) input of address block 7 (first input of counter 22). This signal at the outputs of the address block 7 at the outputs of counter 22 and multiplexer 26 shows the address code of the second bit of the first read line. This code provides an exit from the RAM 10 of the second digit of the character code.

The address code of the selected read column remains unchanged, and the instruction set unit 5 simultaneously processes a cycle of instructions for reading the second digit of the character code. This process continues until all the lower case bits of the character code for the selected read column are read. After reading each digit of the character code, the counter 22 of the addressing unit 7 and the instruction setting unit 5 are reset to the initial state as in the already indicated recording process.

Upon completion of reading all the code digits of the first character read from the RAM 10, the signal from the second output of the switch 4 appears at the second input of the address block 7. At the same time, the address of the second read column is set to the second output group of the address block 7. Thus, the RAM 10 is prepared for reading the second character -. When the shunting code 11 is sent out of the next read start signal, which appears after the formation of the previous sign has been completed, this reading process will be repeated. At the time of reading, signals from the output of the RAM 10 are fed to the information input of the shaper 11 of the code. Shaper 11 in turn generates the necessary code (for example, Morse code or MTC 2 depending on the specific version of RAM 10), which from its output enters the manipulation line of the transmitting device.

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Claims (4)

1. A telegraph code sensor containing a signal input unit, the input and signal output of which are connected respectively to the first and third inputs of the trigger generator, the fourth input and the first output of which are connected respectively to the output of the code generator and to the second input of the first coincidence unit, as well as operational a storage unit and a prohibition element, characterized in that, in order to expand the range of generated code combinations, a switch, an address unit, an instruction installation unit, a multiplexer and the second coincidence unit, the first input and output of which are connected respectively to the output of the operational storage unit and the first input of the code generator, to the second input of which the output of the first coincidence unit, the second input of which is connected to the second input of the second coincidence unit, is connected, to the first input of which the output of the multiplexer is connected, with the third input of the command installation block, with the fifth input of the address block, the signal outputs of which are connected to the address inputs of the operational boot the second input of the switch, the first input of which is connected to the second output of the trigger generator, the first input of which is connected to the first input of the address block, the corresponding signal outputs of which are connected to the control inputs of the multiplexer, and the first output of the switch, the second output which is connected to the second input of the address block, the third input which is connected to the third output of the switch, to the third input of which the synchronization output of the address block is connected, and to the first input of the command setting block, the second input of which is connected to the second output of the trigger signal generator and to the fourth input of the addressable block, to the sixth input of which is connected the first output of the command installation block, the second and third outputs of which are connected to the command inputs of the operational storage unit, to the information input of which the output of the prohibition element is connected, quarter th output block of the commands is connected to the first input of the first block matcher, the code outputs the signal input unit connected to data inputs of the multiplexer. 2. The sensor according to claim 1, characterized in that the switchboard contains two delay elements, two matching blocks and an collecting unit, to the inputs of which the outputs of the delay elements are connected, to the inputs of which the outputs of the matching blocks are connected, the second inputs of which are combined, the first inputs The first and second blocks of the match are the first and second inputs of the switch, respectively, the third input, the first, second and third outputs of which are respectively the second input of the first match block, the output of the first delay element, movement of the second delay element and it vkod gatherer unit. 3. The sensor according to claim 1, characterized in that the command setting unit comprises a distributor, three collecting elements and a generator, the output of which is connected to the third input of the distributor, the second input of which is connected to the output of the first collecting element. 61127. 8 wherein the first input of the distributor and the inputs of the first collecting element are respectively the first, second and third inputs 5 of the instruction setting block, the first, second, third and fourth outputs of which are respectively one output of the distributor, the outputs of the second and third collecting elements, the inputs of which are connected to the other outputs of the distributor, and the corresponding input of the second collecting element. 4. The sensor according to claim 1, about tl and 5 that the address block contains three counters, a coincidence element and a multiplexer, the outputs of the second and third counters are connected to one input, the first The inputs of which are combined, and the inputs of the matching element are connected to the second input and the corresponding outputs of the first counter, the second input of the second counter, the second input of the third counter, the first input of the first counter, the other inputs of the multiplexer and the second input of the first counter, respectively, second, third, quarter,  the fifth and sixth inputs of the address block, whose signal outputs are the outputs of the first counter and the multiplexer outputs, and the output of the coincidence element is 35 synchronization output address block. 25 (play Z FIG 3 Editor S. Lisin Compiled by A. Moskevich Tehred I.Popovich Order 5246/58 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A.Zimokosov