SU474847A2 - Logical memory - Google Patents

Description

37 read formakers, address forms 11r01vat € L11 38 records, control bus 39, strobe bus 40, read amplifiers 41, regeneration regenerator 42, regeneration register triggers 43, reset bus 44, fan 45 regieratsi, address-address ventilators 46 and exits 47 reading units.

Elementary logical operations (dis::;.:; :: i i, conjunctions, right ;, prohibition, and D1; e) 1HY1IOL: HL1OTS when applying a control signal and one of the spike 20-23 of the H11I control. In this case, the operands are the input word X (Xi, ..., Xi, ..., Xn) and some word (or Words) F (K ,,..., F, -,.., K ") , recorded in a line of 2 (or likenka). accumulators /, with the Xi-th-th discharge of the input layer iBa, lran u1, and t-th trigger 14 fergistra / ra 13 glory; W; - / th discharge d - glory, X run w,; ice in the / - th heart | Ke 3 h: i | of the straight line 2 nakp.litel 1, n - the number of bits. The triggers 34 of register 33 iHpn HaKOB of addressing the numeric string in which the operation is to be performed are set to one state H i.

The operation of the logical multiplication of matrices of binary symbols (Boolean matrices) is performed in two ethanes: on the first ethane, the matrix A is transposed;

O-irades of the Leoped mind: the scapes of the Boolean-matrices A and B are defined as follows;

L 0 5 С, where С; y Va, i ,, bkj.

h

The transposition of the matrix of binary symbols A is defined similarly to the aperac H and the transposition of ordinary matrices.

A i: .3 s, where С / у "; /.

The operation of the proposed logical memory in the execution of the logical multiplication operation of Boolean matrices but it is, for example, for d / square matrices with the number of rows and a pillar equal to n.

At the first stage of performing the logical multiplication operation of the Boolean matrices L and B, the matrix L. is transposed. In the initial state, the matrix L is written in n consecutively arranged numerical lines 2 of the accumulator /, starting with some Ctha numerical line 2, where a, - (t 1, 2, ..., p) for the convenience of describing the functioning of this logical device are indicated by the h-isl line 2 of the accumulator /, in which the rows of the matrix L are written first, and the ti row of the matrix L and condition / -Th core 3 of the AGO of the numerical ruler 2 of the accumulator / corresponds to the value of the element a, -j of the matrix L. The matrix B is written in l successively arranged h-isl rulers of the 2-accumulator 1, starting with some Pth numeric ruler, 2 through p, - (/

 12, . . .,) Denotes numerical lines 2 of accumulator / in which the rows of the matrix B are originally written, whereby the 2nd row of the number 2 of the accumulator / corresponds to the rth row of the matrix B, and the state of the /th core 3 of the 2nd row and the corresponding row 2 .wells the value of the element 6, -j of the matrix B. The bit valve 17 is set iB to the initial position (signal at the first output) by applying a control pulse to

bus 18 initial set-to ;. Triggers 43 of the region 42 are registered, set to zero position, trigger 34 regisgras 33.Account 1B reversed and corresponding to the ara H; and, p. 1 lpney.kle 2, - s state "1, and the rest of the triggers 34 of the register of the 33 signs of circulation are in the zero state. The first n numerical lines 2. The accumulator / are cleaned (the cores 3 of these numerical lines 2 are in the state "O").

Transpose boolean

L matrices are produced in n cycles, each of which includes a number of cycles. The g / ohm of qi, glue is carried out by translating the k-OR lines of the matrix. Cycle breaks

on the following measures:

The first clock is reading the row of the matrix on the register 42 of regeneration.

For this, a control signal is sent to the control transducer 24.

element 29 OR and through elements 11 OR to start the read shaper 10. At the same time, through the control element 29 OR and through the A. address valve 36, that address read driver 37 is started, the input of which through the address (vantile 36 is connected to the trioher 34 of the register 33 of the circulation characteristics, which is in the state "1. under the action of the address and bit half-currents, information is read from the corresponding numerical ruler 2 of the accumulator /, and on the reading 6 digits, when switching the cores 3, which are in the IB state "I, output signals that, when a control pulse is applied, on shiiu gate 40 through amplifiers 41 provided to the read -Log setting to '1 triggers register 43 42 regeneration.

Second cycle - clearing the register 33

signs of reversal.

For this, a control signal is supplied to the reset bus 32, which is fed to the inputs of the installation in the "About three-register 34-register 33 O1-rotation" signs.

The third clock cycle is to transfer the contents of the regen regener 42 to register 33 when: 3.

For this, a signal is sent to the control 1CS-inu 39, resulting in: the outputs of the bit-address ventilation 46, the inputs of which are connected with the outputs of the regeneration triggers 43 of the regeneration 42, which are in a single state, and output signals that, through address elements 31 OR, arrive at the inputs of the installation in " 1 of the corresponding triggers 34 of the register 33 of the circulation characteristics.

The fourth cycle is the recording of the -th row of the matrix A in the vth class of the first n number lines 2 of the accumulator.

For this, a signal is supplied to the control bus 26, coming through the Askirov 30 M valve, the signal input of which is connected to the excited output of the bit distributor 17 and the // OR element to start the corresponding bit driver 9 of the record. Simultaneously, through the control element 29 OR and address gates 36, those address shapers 38 are recorded, the inputs of which through the address gates 36 are connected to the direct outputs of the triggers 34 of the register 33 of the characteristics which are in the state 1. At the same time, those cores 3 numerical lines 2 lacopitels /, which are affected by the address and bit half-currents, switch to the IB state "1.

Thus, as a result of this tact in the k-oM cycle, the nth row of matrix A is transposed, i.e. the state of the 3 k-oro cores of the first n number lines 2 corresponds to the values of the elements k-o & rows of matrix A.

The fifth cycle is the clearing of the regeneration register 42 and the register of 33 circulation characteristics.

To do this, a control signal is supplied to the reset buses 32, 44, which are fed to the inputs of the installation in the "On triggers 34 of the register 33 of the access indications and the triggers 43 of the regeneration register 42.

The sixth cycle is the analysis of the completion of the transposition of the matrix A, the preparation of the discharge distributor 17 and the register 33 of the distribution code. 33: And for the next cycle.

In the considered case of square matrices with the number of rows and columns equal to n, the sign of the termination of the matrix A transposition is the presence of a signal on the last output of the bit distributor 17. (In a more general case this sign should be formed in the control unit). To transpose the next row of the matrix L, one performs the next cycle, which is performed by setting the trigger register 34 of the reference sign 33 corresponding to 4 + 1 numeric line 2, where k is the cycle number, in single state by inputting the signal 35 of the register 33 of 1signs of the access and supply of the control pulse to bus 19, as a result of which the output signal of the bit distributor 17 switches from k-opo to (-f 1) -th output.

Ori the presence of the signal of the translocation of the matrix A (signal at the nth output

bit distributor J7) is susceptible

the control pulse to the bus 18 of the initial installation of the bit distributor 17.

Thus, at the end of the first stage of the lottery multiplication operation of the Boolean m-Atritsa A and B, the first n lines of the drive 2 of the drive 1 appear to have transcribed matrix lines written.

In order to perform the second stage, the first p numeric lines 2 of lacolite 1 are released, which is carried out by forwarding the ML to the numerical ruler 2 of the accumulator / in which the matrix L was originally recorded. Since the transfer follows (directly after the transposition of matrix A, triggers 34 the register 33 is turned back, 11 and the Tpiirrepbi 43 of the register 42 of the regeneration are in the zero state; the bit distributor / 7 is in the initial state (the first output is excited), and the cores 3 with an aga in a, g-th numeric lines 2 inclusive - in OI. A. The transfer of the matrix A is performed in n cycles (in the fe-oM cycle, the matrix A is sent / r), each of which includes the following clock cycles:

The first measure - setting the address of the next line Matrix L

For this, the corresponding input signal is supplied to the input 3 of the 5-register of the characteristics of reversal, which drives the A-th trigger 34 of the register of 33 signs, turning into the state "1.

The second clock is the reading of the fe row of the matrix L la register of regeneration.

It is performed similarly to the first cycle of the transposition stage of the matrix L by locking the signal onto the control bus 24..

The third measure is the clearing of the register of 33 circulation signs.

To do this, a control signal is supplied to the reset bus 32, which is fed to the inputs of the installation in the "About Triggers 34 Register 33 Prize (circulation cards ..:,

The fourth cycle - setting the address of the ag; -th number line 2.

For this purpose, an input signal is applied to the inputs 35 of the register 33 of the accessibility signs, which sets the trigger. 34 registers 33 characteristics of circulation, corresponding to a numerical line 2 of accumulator 1, to one state.;.

The fifth bar is to write the k-one of the row of the matrix L to the Ouch NUMBER: line 2 of drive 1.

For this, a signal is supplied to the control width 27 supplied through those regeneration gates 45, the signal inputs of which are connected to the direct outputs of the trigger 43 of the regeneration register 42, which are in the state "1," on the outputs of the elements 11 OR, and .c from the outputs of the latter - to launch the corresponding bit shaper 9 of the record. .At the same time, through the control element 29 OR and the address gate "36 signal input

which is associated with -Gyms - :, g by trigger output 3 of register 33, sign. In circulation, which is In State 1, triggering sg /, Twe T: Start, its address form-iroz-aggel 38 occurs. At the same time, the cores of the hectare of the line 2 of the accumulator, /, on which the address and discharge half-currents go, lg; to: l1Ocha10ts to the state "1. Thus, the .3 result of performing this cycle in the k-sM cycle in a / t-ofi Number Line 2 will appear as k-al, the row of Flatr Schy A.

The sixth cycle - register register 33 lrznak-av processing-nn, clean. repist-rl 42 pei-generation, agNalnz of the endpoint of the Late 5's syntax L.

For this purpose, a control signal is provided to buses 32 and 44, which are reset, nocTynatomiui to the inputs of the circuit,} are in the “About Trigger-aa 34 register 33 sign of circulation and trigger” 4-3 regeneration 42 register. At the same time, the analysis of the end of matrix A transfer is completed (this is the case of iHa signals) The last output of the low-level distributor 17}, in the absence of which a control pulse is fed to the bus - / P, converting the output siplal of the bit distributor 17 s / g on the (k + 1) output. If there is a sign of an aholichi forward: by 11 mafrases L DYUD, a control signal is sent to the M bus of the initial ycTaiHCJBixM. raz1r 1Dog rasp | p dallus h 17.

So. However, by the end of the transfer of the matrix L, the latter is recorded in the numerical rulers 2 of the accumulator / s Aira according to the cn-th numerical Linear 2, It is valid, the grayings of the 3 first n numerical lines of the 2-accumulator} are in the state "O Interpreter 17 - in the initial state of the AI (excited: n "rvy. Exit), and triggers 34 (register 33 iipH3. O1b; SCREEN triggers 43 of register 42 (regeneration is set to the zero state. From this moment begins (second STain ( ВЬ polneN | And oparats; Mn logical multiplication of Boolean 1mat.itsy L on Boolean matrices in B, also carried out sa n cycles, each (of which includes the next nine cycles;

The first step is to set the address of the al-OWN NUMBER line i2.

It is performed in the same way as the fourth cycle of the matrix L transfer cycle when applying to the inputs 35 a register 33 of the circulation characteristics of the corresponding signal.

The second clock is the reading of the k-ofi row of the L matrix. On the regeneration register 42.

It is performed in the same way as the first cycle of the trans-matrix stage A of the matrix A when supplying the control bus to the control bus 24 and the bus 40 of the gate.

The third one; kt - clearing the register of 33 prizes.

It is performed in the same way as the second cycle of the transposition stage of the matrix L when the control signal is applied to the reset bus 32.

The fourth stage is the transfer of the contents of the register 42 of regeneration to the register 33 of circulation characteristics.

It is performed in the same way as the third cycle of the transposition matrix of the matrix .4 when the signal is applied to the control of the bus 39.

The fifth cycle is clearing the register 42 of regeneration.

To do this, a control signal is supplied to the reset bus 44, which is fed to the inputs of the plant in the Registers 43 regeneration register 42.

The sixth cycle - setting the address of the R-th

-2 line. For this, an input signal is supplied to the moves 35 of the register 33 of the indications of circulation, which sets the trigger 34 of the register 33 of the prize conversion rates, corresponding to the Pfe number line 2 to “0 power 1,” to the unit state.

The seventh t and iK t - count the th th

rows of matrix B to register 42 regeneration.

It is performed in the same way as the first cycle.

the ethane cycle of transposition of the matrix A,

with the only difference that the control signals are fed to the bus 25 and also to the gate 40 bus. This makes it possible not to start up the address forwarders 37 for reading those first lines of the two accumulator lines 2, which correspond to the triggers 34 of the register 33, which are in the unit state, which is the case when equality is equal to one. the corresponding elements of the kth lines of the mat: f. L recorded on the register of 33 signs of circulation in the fourth cycle of the given π loop.

Thus, as a result of the first seven clock cycles of the second stage of performing the logical multiplication operation of the boolean

matrices A and B, the i-oro state of trigger 34 of the register of 33 Circulation Signs will correspond to the value of the element of matrix A equal to the element a / y of the matrix A, and the state of the trigger is 43 / -th bit of the register 42 regeneration-value of the element bhj of matrix B.

The eighth cycle - getting pairwise

1Co.nju (NK, tions Between all the elements, th

matrices of L and all elements of k-one

rows of matrix B.

For this purpose, the Signal: is sent to the control bus 27, coming through those regeneration valves 45, the signal inputs of which are connected to the other outputs of the trigger 43 of the regeneration register 42, which are in the same, raw state, and through the circuits // OR to start the corresponding bit shaper 9 records - at the same time through control elements 29 OR and through those address wired 36, signal inputs

which are coupled with the right 1MY; and the outputs of the trigger 34 of the register 33 (recognizing that they are turned into 1), the 1 Core corresponding to the OWN address writing drivers 38 is started up. At that, only those cores of the 3 number lines 2 are switched. , naivoiv111- bs. in cocTOHiHiiiH "About, which are affected by A. drson and; the diluted lolugoki, and those ss: 5 days; n: 11ki, who find themselves in STATE:;.:" 1, do not replace it. Ta .k as i-addressable; (forms; 1: oo, the holder of 38 records is excited by 3 given such cycles of IBc-mn only 3 cases when the element of ac-matrices A (equal to the element a /, the matrix A) is unpd / gcitse, and the discharge shaper 9 of the record / -th bit is excited in a yes: nNOL1 tag of the ft-oro cycle in that and only . in the case when the element bhj of the matrix B is also equal to the unit: its, the signal of the key to the unit, the unit of the unit to the core of the 3 / -th bit of the t-th part of the line; ki 2 (accumulator / (i.e., the ad-temporal excitation of the go address address form; the iroWater 38 record and the bit generator of the 9th decimal and / -th bits) will correspond to the value of the conjunction a: /, bi, i.

In addition, as a result, a given row in the / rth cycle of the matrix B line will be added to (3/2 th numeric line 2, from where it was on the seventh cycle of this cycle). as the trigger 34 of the register of 33 indications of circulation, corresponding to the rh-h; islova lineke 2, as a matter of fact, the execution of this (eighth) cycle is in the state "1.

The ninth clock is the clearing of the register of 33 signs. Turning, clearing the register of regeneration 42, aaa.tyz from the end of the operation of the locksmith umpawa; the bubbling matrix A to the boolean matrix B.

It is performed in the same way as on the sixth cycle of the DI-class of transfer of the matrix L by means of supplying control (Ogn.alovs "and 32 meters 44 faults and, in the presence of an acknowledgment of the end of the operation: on: the last output of the bit distributor 17}, on the bus 18 of the initial installation of the bit distributor 17, and in its absence - on the control bus 19.

Thus, as a result, the second stage of oleration and logical multiplication of the Boolean matrix A by the Boolean matrix B is in the 1 core state, in 3 j-oro bits of the g-th numerical line 2. Accumulator 1

one

will match the value of V aikbin,

l l

That is, in the first hectares of the line 2 of the accumulator, the rows of some Boolean matrix C will be drawn, which is, by definition, the results of performing a logical multiplication operation of the boolean matrix A by the boolean matrix B.

Subject invention

20

Logical capturing device for auth. St. N ° 226681, characterized in that, in order to expand the area 1 in 1 mbnenie, it contains a bit-distributed distribution; the mask, the mask valves, the address-address gates and the address elements OR, the outputs of the discharge distribution valve are connected to the signal by the inputs of the mask gates, to the control inputs of which the corresponding control bus is connected, and the outputs of the masking valves are connected to the OR elements, the signal inputs of the address-address gate valves are connected to the direct outputs of the register trigger (regeneration,

the control inputs of the address-directed gates are connected to the corresponding control bus, and the outputs of these gates are ches the address elements OR are connected; 1Y to the single inputs and triggers of the n.p i3 iak register.