SU1656538A1 - Device for digital unit functional control - Google Patents

Abstract

The invention relates to digital computing and can be used to control high-speed digital logic blocks. The aim of the invention is to increase the testing speed and save the device memory by using the compressed form of the dough package. The device comprises an information input unit, a control unit, a buffer memory unit, a switch, a comparison unit, an information output unit, a test mode setting unit, a shift register unit. 2 hp f-ly, 7 ill.

Description

The device relates to digital computing and can be used to control high-speed digital logic blocks.

The aim of the invention is to increase the speed of testing and save the memory capacity of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block buffer circuit diagram; in fig. 3 - switch diagram; in fig. 4 is a control block diagram; Fig. 5 shows a block diagram for setting a test mode; in fig. 6 is a block shift register diagram; in fig. 7 is a diagram illustrating the principle of positional and concise test packaging.

The device (Fig. 1) contains an information input block 1, a buffer memory block 2, a switch 3, a compare block 4, a guide block, an information block 6, a test mode setting block 7, a shift register block 8, a control object 9 (OK ).

The block 2 of the buffer memory (Fig. 2) contains sub-blocks 21 ... 2k of memory, the number of which is equal to the number K of the input-outputs (channels) of the device. Each subunit contains a RAM 10, an address counter 11, a delay element 12. In addition, block 2 contains the element OR 13.

Switch 3 (Fig. 3) contains switching cells 3i ... 3, the number of which is equal to the number of device channels. Each cell contains the trigger 14 input-output, input key 15, output key 16, elements And 17 and 18.

The control unit 5 (FIG. 4) contains a decoder 19, a test sets counter 20, a comparison circuit 21, a controlled generator 22, a register 23 for the number of test sets, a device operation mode register 24, a channel address register 25, a distributor 26, a first frequency divider 27 , the second frequency divider 28, the switch group 29, the start button 30, the start driver 31.

Unit 7 for setting test modes (Fig. 5) contains nodes 71 ... 7k for setting modes, the number of which is equal to the number of channels of the device. Each node contains a counter of 32 repetitions, a trigger 33 for a sign of testing, a trigger 34 for reloading, a delay element 35, and elements 36-39. Elements OR 40-42.

Yo

0

ate about eating

00 00

Block 8 shift registers (Fig. 6) contains modules shift registers 81 ... 8k, the number of which is equal to the number of channels of the device. Each module contains shift registers 43, 44 of element OR 45, elements of And 46, 47.

FIG. 1-6 depict lines and groups of links.

Line 48 of communication between the first output of the control unit 5 and the launch input of the unit

1 enter information for transferring from the shaper 31 a start command.

The communication group 49 between the second group of outputs of the input unit 1 and the group of information inputs of the control unit 5 for transmitting control commands to the test set counter 20, register 23 of the number of test sets, controlled generator 22, mode register 24, address register 25.

The group of communications 50 between the first group of outputs of the input unit 1 and the group of information inputs of the block 2 of the buffer memory, via which the instructions to zero the address counter 11 and test words for recording and the RAM cell 10 are transmitted.

A communication line 51 between the output of the buffer memory unit 2 and the start input of the control unit 5 for transmitting the Start command from the output of the OR 13 element to the starting driver 31.

The group of communications 52 controls between the first group of outputs of control unit 5 and the group of control inputs of buffer storage unit 2 for transmitting from decoder 19 and group of switches 29 to RAM 10 of the Write - read command and Write signal, respectively.

The group of communications 53 between the third group of outputs of the control unit 5 and the control group of the inputs of the unit 7 for setting test modes. In test mode, the clock signal is transmitted from the output of the controlled generator 2 to AND 36, the signal from divider 27 to AND 38 in the positional form of test packaging, the signal from divider 28 to And 37 in compressed form of the test packaging.

The communication group 54 between the first group of outputs of the buffer memory block 2 and the group of information inputs of the test mode setting unit 7 for transferring test information from the RAM 10 to the repetition counter 32 and the test sign trigger 33.

The group of communications 55 between the first group of outputs of the block 7 setting test modes and the group of control inputs of the block

2 buffer memory for signal transmission Increase the address from the OR 40 element to the 12 delay element.

The communication group 56 between the second group of outputs of the buffer memory unit 2 and the group of information inputs of the shift register unit 8 for transmitting test information

from RAM 10 to shift registers 43 and 44.

The communication group 57 between the second group of outputs of the test mode setting unit 7 and the group of control inputs of the block 8 shift registers for signal transmission Record from the inverted output of the reset trigger 34 to the control inputs of registers 43, 44. of the signal Shift from the OR 41 element to the synchronous inputs of registers 43, 44, signs of positional and compressed dough packing forms from the direct and inverse outputs of the trigger 33 to the inputs of the And 47 and 46 elements, respectively.

The group of communications 58 between the group of outputs of the block 8 of the shift registers and the group of information inputs of the switch 3 for the transfer of tests (standards and stimuli) from the output of the register 43 to the elements And 17, 18. The group of communications 59 between the second group

the outputs of the control unit 5 and the group of control inputs of the switch 3 for transmitting the recording signal from the switch group 29 to the inputs of the respective flip-flops 14, as well as for transmitting the prohibition signal to the keys 15, 16 from the decoder 19.

The group of communications 60 between the group of outputs of the switch 3 and the group of information inputs of the unit 4 of comparison for transferring the standards from the elements AND 16 and the reaction OK with

the outputs of the keys 15 to the corresponding channel elements of the comparison block 4.

The communication line 61 between the second output of the control unit 5 and the input end of the testing of the information output unit 6 for

signal transmission End of test from the comparison circuit 21.

The communication group 62 between the group of outputs of the comparison unit 4 and the group of information inputs of the information output unit 6 for transmitting the signal of the results of the comparison of standards and OK.

Channels 63 of the device for communication with the outputs (inputs, outputs) OK.

The communication line 64 between the third output of the control unit 5 and the control input of the comparison unit 4 for transmitting a signal Interrogating the result from the generator 22 to the comparison elements of the unit 4.

Communication lines 65 from the output of the comparison unit 4 to the stop input of the control unit 5 for transmitting a generator stop signal 22. The information input unit 1 is intended for inputting, for example, test paper of control information from a punched tape. The test consists

from testonaborov, each of which contains incentives and standards. Incentives - a set of signals applied to the inputs of OK9. Standards - a set of signals that should appear at the outputs of the OK 9 in response to stimuli, if the OK is in good condition. The control information determines the operating mode of the device, the addresses of the initial and final test sets, the output functions (input, output) OK, the supply of general control commands. The input block 1 links the outputs with the blocks 2, 5, and the inputs with the block 5 controls.

The buffer memory unit 2 is designed to receive test kits from unit 1, store them and deliver them to blocks 7, 8.

The switch 3 divides the device channels to the inputs-outputs, in accordance with this, the stimuli arrive at the inputs of OK9, and the reactions from the outputs of OK 9 and the standards from the outputs of block 8 of the shift registers arrive at block 4 of the comparison.

Comparison unit 4 compares the standards with reactions and transfers the comparison results to information output unit 6. In addition, in case of rejection, the comparison unit 4 stops the operation of the device by applying a signal to the control unit 5.

The control unit 5 serves for storing control information and issuing control signals in blocks 1-4, 6, 7.

The information output unit 6 serves to print the results of the control.

The test mode setting unit 7 is designed to control the operation of the unit 8 depending on the form of the test package.

The shift register unit 8 converts a parallel code from block 2 of the buffer memory into a serial code.

RAM 10 is intended for receiving, storing and issuing test words. A test word is an (s + 1) -bit binary code, the least significant bit of which is assigned to the sign of a positional or compressed form of test packing. In addition to the indication of the shape of the package, half of the least significant bits of the word are allocated to the number of repetitions under compressed form and under test kits with the positional form of the test package. Half of the high-order bits of the word are reserved for test kits, regardless of the shape of the test package.

FIG. 7 shows an example of a T test for OC having two outputs 1 and J. A test T, respectively, of the conclusions contains two elementary tests Ti and Tj, simultaneously it consists of 48 test kits, the numbers of which are designated as NTH. First test on

five

boron in test T, taking into account the order of the following - conclusions 1 and J, has the form 11, the second - 01, etc. Test T is written in 9-bit test words. Every 9th (minor) bit of test words contains a sign of the word packing. If the sign is equal to 1, the test word has a positional form of the package, otherwise a compressed form of the package. FIG. 7 and all the words of the test T contain only the positional form of the package. FIG. 7 b the words of the test T are written in both compressed and positional form. To simplify the recording form of the test T in FIG. 7b is named as compressed in spite of the fact that it contains words in two forms of notation. In the positional form of recording test words, all bits from the 1st to the 8th contain test kits, and when compressed, bits from the 5th to the 8th inclusive contain the number of repetitions of the code recorded in the higher bits from the 1st on the 4th

With the compressed form of the test T (Fig. 7 b), the elementary test TI consists of four words, while the test sets from the 1st to the 8th and from the 29th to the 36th are written down in a positional form, the rest of the test sets in compressed form. Thus, the test kits from the 9th GRPO 28th are recorded in the form of a five-fold ITE repetition code 1011, the test kits from the 37th to the 48th in the form of a triple | 00 1 g repetition of code 0000. The elementary test Tj consists of two words, while the test kits from the 1st to the 40th are recorded in the form of a tenfold 1010 repetition of the code 1111. and the sets from the 41st to the 48th in the positional form .

With the positional packing form of the test, the number (s + 1) of the bit cells of RAM 10 necessary for recording the elementary test Ti is equal to

P

m - s

where n is the number of test kits.

When compressed form of packaging is the same number

m P. s

For the elemental dough Ti shown in FIG. 7, s 8; p 48; m 6; m 4.

The older half of the test word bits from RAM 10 are fed to the information inputs of the shift register 43 of block 8, the younger half of the bits go to the information inputs of the shift register 44 of block 8 and the counter of 32 repetitions of block 7, the youngest (s + 1) -th bit arrives 5 to the information input of the trigger ZZ of the sign of testing the block 7.

The address counter 11 serves to form the addresses of the RAM cells 10.

The delay element 12 is designed to form a time interval between 0

five

0

five

0

five

0

do write-read information from RAM 10 and increase the code in the counter 11 addresses.

The I / O triggers 14 separate the readable test information from block 8 into stimuli and standards and identify the findings of the OK 9 into the inputs and outputs.

Input keys 15 are designed to transfer reactions from the outputs OK 9 to the inputs of unit 4 of the comparison.

Output keys 16 are designed to transfer stimuli to the inputs of T OK 9.

The decoder 19 of the control unit 5 is designed to form control commands in the units 2, 3, the counter 20, the distributor 26, the launch driver 31.

Test set counter 20 counts test sets in test mode and test words in recording mode.

The comparison circuit 21 compares the contents of the test set counter 20 and the register number 23 of the test sets to which either the number of the last test set (test mode) or the number of the last test word (record mode) is entered.

The controlled generator 22 is designed to form single pulses in the recording mode, fed to the distributor 26, and a series of clock pulses in the testing mode, fed to the inputs of frequency dividers 27, 28, to the counter 20 and the inputs of the comparator unit 4, the unit 7 to set the testing modes.

The device operation mode register 24 is intended to receive the operation mode code from the information input unit 1. The mode code controls the decoder 19.

In the channel address register 25 of block 1, the positional code of the output OK is entered. The number of register bits 25 is equal to the number of device channels.

The distributor 26 is designed to form in the recording mode single pulses in the buffer memory unit 2, in the test mode setting unit 7, in the switch 3.

The first and second frequency dividers 27, 28 are designed to form signals, respectively, with the frequencies f / s and 2f / s in the test mode, where f is the frequency of stimulus output per OK.

The switch group 29 switches the pulses in the write mode in accordance with the contents of the channel address register 25. The number of switches 29 is equal to the number of channels of the device. The output of each switch 29 is connected to the inputs of the respective subunits 21 (RAM 101) of block 2, cells 31 (flip-flop 141) of switch 3, nodes 71 (circuit

OR 401) of block 7 setting test modes.

The start button 30 forms the device Start command.

The launch driver 31 is designed to start the block 1 to enter information. The repetition counter 32 of block 7 is designed to receive the service part (repetition number code) from the RAM 10 of block 2 when compressed

0 form of packaging dough.

The trigger 33 of the test feature is a D-type trigger, intended for receiving the (s + 1) th minor bits (packing feature) from the RAM 10 of block 2, performs control in blocks 7 and 8 of the test organization with positional and compressed forms packaging dough.

The reset trigger 34 is an RS-type trigger that controls the mode of operation.

0 shift registers 43, 44 in block 8.

The zero state of the trigger 34 corresponds to the parallel recording mode, the single state to the shift mode.

Delay element 35 is intended

5 to form a time interval during which the test word is written in parallel to the shift registers 43, 44, the repeat counter 32, and the trigger 33. The registers 43, 44 of block 8 represent

0 shift registers with parallel recording of information are intended to receive test information from RAM 10 and output it to switch 3.

The device works as follows.

5When power is on, the trigger 14

the inputs / outputs in the switching cells of the unit 3 are set to the initial (zero) state, the test indication triggers 33 and the reset triggers 34 in the nodes 71

0 of the block 7 for setting test modes - to one state, the first 27 and second 28 frequency dividers to the state 11 ... 1. Installation inputs are not shown. When you press the button 30 in block 5 control signal with

5 of the output of the start 31 of the communication link 48, the information input block 1 is started.

0 communication group 52 to the control inputs of all the RAM 10 of the buffer memory unit 2 and sets them to the write mode. The same signal from the decoder 19 in the distributor 26 establishes a direct connection between its

5 outputs and the output of the controlled generator 22, the operation of the counter 20, the generator 31, and through the communication line 59, the input keys 15, the output keys 16 of the switch 3 are set to the high (third) state, that

provides OK and device output during recording mode. Continuing to arrive from block 1 information through a group of links 49 nulls the counter 20 test sets and registers 23, 25, and through a group of links 50 nulls the counters 11 of the address of all sub blocks of the buffer memory 2. Then from block 1, according to the group of communications 49, one is entered into the corresponding register register 25 of the address. The unit state of this bit closes the corresponding switch 29 from the switch group 29, and the register 23 records the number of the last loaded test word corresponding to the channel specified in register 25, and hence the subblock 21 in memory block 2. After that, controlled by generator 22 is launched from block 1 through communication group 49. The pulse from generator 22 increases the contents of the counter 20 test sets by one, and through distributor 26 simultaneously arrives at all inputs of switch group 29. This pulse through switch 29i is prepared by the contents register 25 through the communication group 42 enters the synchronous input of the RAM 101 of block 2. By this time, the first test word is set on the information bus of the communication group 50 from block 1, which is entered into the RAM 10 at the zero address of the counters 11. One alternately with switches 29, the impulse from generator 22 goes through a group of connections 53 to elements OR 40 of block 7, and from their outputs through a group of connections 55 to elements 12 of delays of block 2. Pulses from the outputs of elements 12 of delays increase the contents of counters 11 per unit and simultaneously through the OR element 13 of block 2, via the communication line 51, a trigger signal is sent to the control block 5 to the starting driver 31. Again, from the output of the trigger generator 31, via communication line 48, block 1 receives a trigger signal, via which the next second test word is set on the information bus of the communication group 50, a. according to the group of communications 49 from block 1, controlled generator 22 is launched. By the second impulse from controlled generator 22 of block 5, this word is written into RAM 101 of subunit 21 at the next address, etc. Writing information to the subunit 21 of the buffer storage unit 2 continues until the state of the test set counter 20 becomes equal to the contents of the register 23. If the output of the comparison circuit 21 of the unit 5 is equal, a pulse will appear that will inhibit the operation of the generator 22 and sets counter 20, register 25 and register 23 to the zero state. Further in register 25 from block 1 is entered

address of the next channel, and in register 23 -. the number of the last loaded test word in the subunit of block 2 of the selected channel. The loading of the next subblock of block 2 takes place similarly to the previous one, etc., until all the subblocks of the block 2 of the buffer memory necessary for this OK are loaded. After loading the block 2 with the dough into the register 24 of the block 5 from the block 1 according to the group

connection 49, a code is recorded which, via decoder 19 and communication line 59, confirms the high-impedance state of keys 16, 15 of switch 2. With the same signal from decoder 19, distributor 26 is switched to sequential obegano mode, and the output of controlled generator 22 is connected to input the first cell of the distributor. Simultaneously, the signal from the output of the decoder 19 prohibits the operation of the counter

20. Then, from the information input unit 1, the register 25 of the control unit 5 records information on which triggers 14 of the switch 3 should be set to one. Thereby

the corresponding switches 29i from group 29 are turned on. Subsequently, controlled generator 22 is started from block 1. Each next pulse from generator 22 arrives at distributor 26 and appears at its next output. This impulse, by a group of links 59, will go or not go to this cell 3i at the installation input of trigger 141, depending on whether the corresponding

a switch 291, the state of which is determined by the information of the channel address register 25. The recording of information in the switch 3 is stopped after the occurrence of the signal at the last output of the distributor 26, this signal prohibits the operation of the controlled generator 22.

In the switching cells 31, where the trigger 141 is set to one state of the signals from its direct output, the AND element 17 and the output key 161 are prepared to skip the binary sequence (stimuli) to the OK 9 input from the output of the corresponding shift register 431 of block 8. the inverse output of the same trigger 141 closed

the second element And 181 and the input key 151.

In all other cells of the switch 3, where the trigger 14j is set to the zero state, on the contrary, the element 18j and the input key 15j are prepared to skip the binary sequences. The first of them passes the test standards from the output of the corresponding shift register 43J of block 8, and the second, the reaction from the OK 9 output to the inputs of the corresponding comparison circuit (not shown) of block 4. Element And 17J and output key 16 are closed.

It is necessary to note once again that in the information recording mode all keys 15 and 16 of switch 3 are closed, or rather they are in a high-impedance state, which is determined by register code 24 and a signal from decoder 19.

After loading the RAM 10 of the unit 2 and the triggers 14 of the switch 3 into the mode register 24, the information is entered from the information input unit 1, which determines the OK testing mode. This code through the decoder 19, the communication group 52 sets all the RAM 10 of the block 2 signals at their control inputs into the read mode. The same signal from the decoder 19 prohibits the operation of the distributor 26. And at the outputs of the keys 29, a high level signal is set, which is fed through the communication group 52 to the synchronous inputs of all the RAM 10. The same code of the register 24 prohibits the operation of the launching device 31, and by the group of links 59, the high-impedance state of the keys 15, 16 of the switch 3 is removed.

Then, the command from block 1 nullifies the counter 20 test sets in control block 5 and the address counters 11 in the sub blocks of the buffer memory block 2, and register 23 of the number of test sets from the same block 1 records the number of the last test set. After that, controlled information generator 22 is started from block 5, which generates pulses with an OK testing frequency. equal to f. On the leading edge of the first pulse from the generator 22, the output of the divider 27 (taking into account its initial state) generates a pulse whose duration is less than the period T 1 / f. This impulse through the communication line 53 enters all nodes of block 7 and through element AND 38 (prepared by the initial state of flip-flops 33), through element OR 42 enters the inputs of reset triggers 34, delay elements 35, and elements OR 40. 41.

The operation of the device is described by the example of one channel. The positive signal from the inverse output of the trigger 34 of block 7, reset by the signal from the element OR 42, through the communication group 57, the shift registers 43, 44 of block 8 are set to parallel recording of the higher s bits of the test word from the RAM 10 of the block 2. placed in the cell a zero address arriving at the registers 43. 44 over a group of links 56. A pulse from the OR element 41 of the block 7 supplied via the links 57 to the synchronous inputs of the registers 43, 44. the specified test word is written to them.

In this case, half of the high-order bits of a word from s are written to register 43, and half of the low-order bits to register 44. At the same time, half of the low-order bits and (s +

1) the lower order bit of the same test word, which enters the group of links 54 from block 2 to block 7, is recorded respectively in counter 32 and trigger 33 on the impulse fed to their sync inputs from the circuit

0 OR 42. Simultaneously with the pulses from the element OR 41, 42, a pulse arrives at the element 12 of the delay from the output of the element OR 40. After writing the first test word from the zero cell of the RAM 10 of block 2 to registers 43, 44. test counter 32 and trigger 33 the pulse from the output of the delay element 12 increases the content of the address 11 counter by one. The same impulse, having reached through the element OR 13 shaper 31

0, does not change the state of the latter, since it is blocked by the register code 24 modes through the decoder 19. Simultaneously with the change in the state of the counter 11, the address of block 2 is set to one

5 is the state of trigger 34 of block 7. This happens when a pulse arrives at this trigger from the output of delay element 35. The single state of the trigger 34 sets the registers 43, 44 of the block 8 to the shift mode and prepares

0 element AND 36 to receive clock pulses from generator 22 of block 5.

Further operation of the device depends on the information read from the RAM 10 of block 2. With a positional form of packaging

5 test trigger unit 33 is recorded unit. The unit state of the trigger 33 prepares the element AND 38. In addition, the single signal of the trigger 33 through the communication group 57 enters the

0 block 8 per element AND 47, by means of which through the OR 45 element from registers 43, 44 one shift register is formed, the number of bits of which is s. Clock pulses (including the first) with frequency

5 testing f from the generator 22 of the control unit 5, according to the group of connections 53, arrive at block 7 on the prepared element AND 36, from whose output through the element OR 41 they arrive at the synchronous inputs of registers 43, 44

0 of block 8 by the group of communications 57. From this moment the working cycle of testing OK begins. The recorded test word from the output of the register 43 in the serial code for the group of communications 58 enters the switch 3 to the inputs of the elements 17, 18. At the same time, with the first clock pulse of the generator 22, the oldest (1st) bit of the test word enters the switch 3 , with the second pulse of the 2nd bit ... with the s-th pulse of the s-th (minor) bit, i.e. from register 43 test word

pushes head forward, Depending on what information is recorded in trigger 141 of this switching cell 3i, the test word enters either through the AND element 171 and the output key 161 to the 1st output OK 9, which is OK 181 through the communication group 60 in comparison unit 4, if the 1st output (Za is an output. On the leading edge of the (i + 1) -th pulse of the generator 22, when the first test word from registers 43, 44 has already been completely transferred to the switch 3, the frequency divider 27 again receives a pulse through a group of links 53 in block 7 at the input of the element And 38. According to this impulse, the next 2nd test word will be written from the RAM 10 of block 2 to registers 43, 44 of block 8, to counter 32 and trigger 33 of block 7. Clock pulses that continue to flow from generator 22 to element 36 of block 7 ( including (s + 1) -th) provide the process of issuing the test to the switch 3, etc.

With the positional packing form of the test word, the signal from the inverse output of the trigger 33 through the elements 39, 37 of the operation of the counter 32 is blocked.

With the positional form of the test word package, the frequency of accessing the RAM 10 is s times less than the test clock frequency f, so in the proposed device one can either use low-frequency RAM, or, as compared to analogues using buffer RAM, as a direct source of test information, increase the frequency testing s times

With a compressed form of packing the dough into the trigger 33 of the block 7 from the RAM 10 of the block 2, O is recorded, as a result of which the elements AND 37, 39 are prepared and through them the counter 32 is ready for operation, the element 38 is blocked. A high level from the inverse output of the trigger 33 through the group connections 57 enters block 8 on AND 46, with the result that the serial output of register 43 of block 8 through AND 46 and OR 45 is connected to its serial input. The code recorded in the counter 32 of block 7 means the number of test repeats recorded in register 43. Register 44 and the code written in it (the same as in counter 32) with compressed packing does not participate in the work, because its output is blocked by the zero state of the trigger 33 of the block 7. Clock pulses (including the first) from the generator 22 of block 5 through the element AND 36 and through the element OR 41 of the block 7 through the communication group 57 arrive at block 8 on the synchronous inputs of the register 43, as a result of which the test information recorded in it

serial code on the group of communications 58 enters the switch 3,

After every s / 2 shifts in register 43, the test, initially recorded from the RAM 10 of block 2, is repeated, since it is closed up by AND 46 and OR 45. At these times, the second divider 28 controls the frequency of control unit 5 by group 53 block 7 on the prepared element and 37

an impulse is received, which subtracts one from the counter of 32 repetitions. The process continues until the state of the counter 32 is zero. In this case, the output of the counter 32 is formed

a pulse with a duration of shorter period T - 1 / f, which passes through the prepared AND 39 circuit and through the OR element 42 resets the reset trigger 34, thereby preparing registers 43, 44

block 8 to the record of the next test word read from the RAM 10 of block 2. The same impulse is fed to the synchronous input of the parallel write to the counter of 32 repeats and the synchronous input of the trigger 33. In addition, through

the OR 42 scheme, this pulse enters the group of communications 57 in block 8 on the synchronous inputs of registers 43, 44, as a result of which the corresponding bits of the next test word from the RAM 10 of block 2 in the group of communications 56

is written to registers 43, 44 of block 8, over a group of links 54 into a counter 32 repetitions, trigger 33 of block 7. Through the element OR 40 over a group of links 55, the same impulse goes to block 2 of the buffer memory per element

12 delays, through which a unit is added to the address counter 11. Through the delay element 35 of block 7, the trigger 34 is set to one, preparing registers 43. 44 blocks 8 to shift the recorded

test information.

Next, the clock pulses again from the generator 22 of the block 5 at a frequency f to the element 36. And the test issuing process continues.

With a compressed form of the test package, the frequency of access to RAM 10 in K C-1 times

less than the test frequency f, where L is the number of repetitions in the counter 32. The physical meaning of the compressed recording form is when L 2, since otherwise it is equivalent in terms of the effectiveness of the positional form. Thus, the minimum value of K is 3 s / 2. Therefore, compared with similar devices that use single-bit buffer RAM as a source of test information, the performance of the proposed device

with a compressed recording form, it is increased at least 3- s / 2 times.

For a given volume of m RAM cells, whose size is equal to s + 1, the maximum test length for a positional recording form in the proposed device is n m - s.

With the compressed form of the dough packing in all the RAM cells, the maximum test length is equal to n - 2. Thus, when compressed, RAM memory is used much more economically.

The pulses from the controlled generator 22 of the control unit 5, in addition to the test task setting unit 7, enter the comparison unit 4 via a communication link 64 and to the counter 20 test kits. The test continues until the state of the counter 20 becomes equal to the contents of the register 23 of the number of test sets. In this case, the comparison circuit 21 operates, the signal with which will prohibit the operation of the controlled generator 22, as a result of which the issuance of stimuli to OK 9 will be stopped. The signal from the comparison circuit 21 also goes to the information output block 6 on the communication line 61, which certifies the healthy state OK 9. At the same time, the pulses from the controlled generator 22, coming to the comparison unit 4 via the communication line 64, gate the comparison circuits of the unit 4 (not shown, their number is equal to the number of OK outputs), which are received through the communication group 60 s of the switch 3 standard From the circuits And 18, as well as reactions from the outputs OK 9 through the input keys 15. The keys 15 are prepared for switching on from the inverse outputs of the trigger 14 input-output outputs that are in the zero state in those switching cells 31, which correspond to the outputs OK 9. In addition, the keys 15 are prepared by a signal from the output of the decoder 19 of block 5 according to the communication group 59, when the test code OK is recorded in the register 24 of the device operation mode.

Incentives for the group of communications 58 from block 8 arrive at switch 3 on element 17, which are prepared from the direct outputs of the flip-flops 14, which are in the unit state in those switching cells 31, which correspond to inputs OK 9. From the outputs of elements 17 stimuli through the output keys 16 are sent to the OK 9 through the group of communications 63.

If the standard does not coincide with the response, block 4 of the comparison generates a signal coming over communication line 65 to stop the controlled generator 22 of block 5, after which the output of stimuli on the OK 9 stops, and the result of the control over the communication group 62 goes to block 6 information.

where the OK 9 fault status and the fault address are reported.

Claims (3)

Invention Formula 1. Device for functional control of digital blocks containing a block input information, buffer storage unit, switch, comparison unit, control unit, information output unit, the first and second groups of outputs of the input unit 0 information is connected respectively to the groups of information inputs of the buffer memory unit and the control unit, the first, second outputs, as well as the first and second groups of outputs of the control unit are connected respectively to the start input of the information input unit, to the input of the end of testing the information output unit, with the group control inputs of the buffer memory block and with the first group of control inputs 0 of the switch having a group of information I / O for connecting the control object, the group of information inputs of the information output block being connected to the output group of the block 5, which, in order to improve speed and save memory, the mode setting block is entered into the device testing, the shift register unit, and the control and 0 information groups of the inputs of the test mode setting unit are connected respectively to the third group of outputs of the control unit and to the first group of outputs of the buffer memory block, output and second 5, the group of outputs of the buffer memory block are connected respectively to the start input of the control unit and to the group of information inputs of the shift register block, the first group of mode setting outputs 0 testing is connected with the group of control inputs of the buffer memory block, the second group of outputs of the block of setting test modes is connected with the group of inputs of the control of the shift register block, 5, the output group of which is connected to the information input switch group, the control input of the comparison unit is connected to the third output of the control unit, the output of the comparison unit is connected to the input input of the control unit, the information input group of the comparison unit is connected to the output group of the switch. 2. The device according to claim 1, characterized in that the test mode setting unit includes mode setting nodes according to the number of device inputs / outputs, each of which contains three OR elements, a repetition counter, a test sign trigger, a reset trigger, four elements And the delay element whose input connected to the setup input of the reset trigger, with the synchronous inputs of the trigger of the test sign and the repetition counter, with the first inputs of the first and second OR elements and with the output of the third OR element. the first and second inputs of which are connected to the outputs of the first and second elements AND, the first input of the second element AND, as well as the first inputs of the third and fourth elements AND and the second input of the first element OR are connected to the first group of control inputs of the test mode setting unit which is connected to the information inputs of the test sign and repeat counter, the subtractive input of which is connected to the output of the third element I, the second input of which is connected to the first input of the first element nta And, with an inverted trigger trigger output and is connected to the second group of outputs of the test mode setting unit, the forward trigger sign output of the testing attribute is connected to the second input of the second element, And the reset input and direct output of the reset trigger are connected respectively to the output of the delay element and with the second input of the fourth element And, the output of which is connected to the second input of the second element OR, and the output of the repeat counter to the second input of the first element I. In this case, the direct output of the trigger of the feature is tested Inverse output trigger reset, and the output of the second OR gate is connected to the second band specifying unit outputs test mode, the output of the first OR gate is connected to the first band specifying unit outputs test modes, 3. The device according to claim 1, that is, that the block of shift registers contains shift register modules according to the number of inputs and outputs of the device, each of which contains an OR element, two AND elements, the first and the second shift registers, the information inputs of which are connected to the group of information inputs of the block of shift registers, the combined control inputs of the first and second shift registers, as well as their combined synchronous inputs, the first inputs of the first and second elements I are connected to the group of control inputs of the shift block flashing registers, the outputs of the first and second shift registers are connected to the second inputs of the second and first elements AND, the outputs of which are connected respectively to the first and second input of the OR element, the output of which is connected to the shift input of the first register whose output is connected to the group of outputs of the block of shift registers . 1 ffl M FIG. five one I " 9 i i 16 P  I U 15 I I And 33 I I liO 4 / I I US I II II II II II I IOIIOIII QJlOl IIOIIQ I0IIIOI101011 lOOflffll I WOOMftOOOOOOOO® iilii | il T llllllll i llimilQ IIIIMII llllllll (Qlll0l IIQ and Positional po / var ynoxobni mec / na NTH 189 26 Z9 36 31 48 r iiiiiiii r loiioni i1ion | oio11lo | ioooiiig ilogflo | jpinia NTH 1 W 4f 48 Ttj & Circuit 5. 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