SU1559297A1 - Device for automatic normalization of binary code - Google Patents

Abstract

The invention relates to a measuring technique and can be used in measuring and computing complexes. The purpose of the invention is to increase the reliability of the device. The device for automatic normalization of the binary code contains the elements OR 1 and 2, the element AND 3, the shift register 4, the shaper 5 pulses, the encoder 6, the triggers 7 and 8, the input 9 of the initial installation, the input "reset" 10 devices, the output 11. the output generates a potential jump, indicating that the selection of the limit has been made. At the same time, at the outputs of the register 4 of the encoder connected to the output bus, an input code is generated that is converted into a standard form. 2 Il.

Description

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The invention relates to a measuring technique and can be applied in measuring and computing complexes

The purpose of the invention is to increase the reliability of the device.

Figure 1 shows the block diagram of the device; figure 2 - timing charts of his work.

The device (figure 1) contains the first 1 and second 2 elements OR, the element And 3, the shift register 4, the pulse shaper 5, the output of which is connected to the counting input of the shift register 4, and the encoder 6, the outputs of which are connected to the output bus of the device, the encoder 6 is designed as a counter, the outputs of the shift register k are connected to the output bus of the device, the first and second triggers 7 and 8.

The first input of the first trigger 7 connected to the input of the element AND 3 is input 9 of the initial installation of the device, the second input is connected to the output of the first element OR 1, and the output is connected to the input of the pulse generator 5, to the control input of the shift register 4 and another input And 3, the combined first inputs of the first 1 and second 2 elements OR are connected with the output of the high bit of the encoder 6, the first input of which is connected to the output of the driver 5 of pulses, and the second input is connected to the output of the second element OR 2, the second input of which is connected with the output of the element And 3, the first input of the second trigger 8 and the installation input of the shift register 4, the outputs of which are connected to the output bus of the device, and the output of the higher order - with the second input of the first element OR 1, the third input of which is connected to the input 10 VA, whose information input is the group of inputs of the shift register 4, and output 11 - the output of the second trigger 8. whose second input is connected to the output of the first element OR 1.

The imaging unit 5 may comprise a generator 12 connected in series and a counter 13 whose input and output is the input and output of the imaging unit 5, respectively.

Figure 2 shows the following timeline designations:

a is the signal at the input 9 of the device; b - the signal at the output of the trigger 7; in - the signal at the output of the imager 5;

output element 3;

the output of element 1;

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e

on on

signal

signal

output signal 11 limit

selected;

W - signal at the output of the Q trigger 8 The device operates as follows.

The C register is written with the code of the number to be converted. If this number has 1 in the high order, the device does not select the limit and the zero code is saved at the output of the encoder 6, i.e. the smallest limit (range number 000) is selected, while trigger 7 remains in state O. If in the highest bit of the recorded code is O, trigger 7 is set to 1, driver 5 is unlocked and register k is shifted 5 5

0

0

lasts until the high potential is established at the output of its high-order bit. At this moment, the choice of the measurement limit is stopped, the code of the number of the selected range (i.e. the number of shifts) is fixed on the encoder 6.

At the initial moment of time, the triggers 7 and 8 are in the zero state (for example, from the Reset pulse, which arrived at the device input 10), the driver 5 is blocked and no pulses are received from its output. The initial setup pulse (figure 2), which came from the device input 9, sets the trigger 8 to the state 1, passes through the open element 3 (fig 2g) to the input A / S of the shift register 4. At this moment, the parallel input mode is organized at the inputs of the register 4 (in accordance with the register state table 4), and the information set at this moment at the information input of the device is recorded in the register 4.

At the moment of the drop (1-0) at the input C of the trigger 7 (by the cut-off pulse of the initial setup) it is set to 1, the AND 3 element is closed and a code is set up at the inputs of the register k, which sets it to the information shift mode. The former 5 is unlocked and the counting inputs of the encoder and register 4 begin to arrive.

50

five

shift pulses (figv). Suppose that after three shifts (Figure 2b) a high potential is established at the input of register b (Figure 2d). At this time, the triggers 7 and 8 are reset (Fig. 26, e). At output 11, a potential jump occurs (1-0), signaling that the selection of the limit has been made. As a result, the outputs of the encoder register k connected to the output bus turned out to be the input code converted to standard form. When the device according to FIG. 1 is executed, information on the bits from 0 to C of the output bus is arranged, and on bits from 5 to 7 the code of the range selected by the device (i.e., the number of shifts of the input code) is located.

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Claims (2)

Invention Formula A device for automatic normalization of a binary code containing the first and second elements OR, the element AND, the shift register, a pulse shaper, the output of which is connected to the counting input of the shift register, and an encoder, the outputs of which are connected to the output bus of the device, characterized in that In order to increase the reliability of the device, the first and second trigger were introduced into it. 1559297 the first input of the first trigger is connected to the first input of the device, the second input is connected to the output of the first OR element and to the first input of the second trigger, and the output of the first trigger is connected to the input of the pulse former 0 input of the shift register and the second input of the AND element, the combined first inputs of the first and second elements OR are connected to the output of the higher one (Bit of the coder, the first input of which is connected to the output of the pulse former, and the second input is connected to the output of the second element OR , the second input of which is connected to the output of the element I, the second input on 0 trigger and the installation of the shift register, while the outputs of the shift register are connected to the output bus of the device, the output of the higher bit of which is connected to the input 5 Device reset, information input of the device is connected to the information inputs of the shift register, one of the outputs of the device with the output of the second trigger. 0 2. The device according to p. Is distinguished by the fact that the encoder is made in the form of a counter. Editor V.Danko FIG. 2 Compiled by A.Romanov Tehred L.Serdyukova Order 836 Circulation VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Proofreader N. King Subscription