SU1525716A1 - Multichannel digital interpolating filter for frequency multiplexing of channels - Google Patents

Abstract

The invention relates to radio engineering and computing and can be used in multi-channel communication devices with digital signal processing. The goal is to expand the scope. The invention makes it possible to additionally form a group signal of frequency-compressed channels due to the fact that a known filter containing a random access memory unit 1 and a permanent memory unit 5 accumulate adders 2 and 4, a first address adder 8, a multiplier 3, a counter 11 sampling and channel counter 6, block 7 of EXCLUSIVE OR elements, first and second counters 12, 13, synchronization block 9 and element OR 10, the second permanent memory block 16, the third accumulating adder 15, the switch 14, the second address adder 17, are entered, address memory block 18, ale Options AND 19 and OR 20. The exclusive-2-yl.

Description

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This invention relates to radio engineering and computing. can be used in multichannel communication devices with digital signal processing

The purpose of the invention is to expand the field of application of the filter by forming an output group signal.

Figure 1 shows the block diagram of the filter; figure 2 - structure, on the diagram of the synchronization unit

The multichannel digital interpolating filter for frequency multiplexing of channels contains a block of 1 RAM, a first accumulating adder 2, a multiplier 3, a second accumulating adder 4, the first permanent memory block, a 6 jJoB counter, a block of 7 elements EXCLUSIVE 1CE OR, the first address adder 8, synchronization unit 5, element OR 10, sample counter II, first and second counters 12 and 13, switch 14, third accumulator adder 15, second () lok 16 fixed memory, second adder 17, memory block 18, slot I 19, IC element KShO-ORGANIZER OR 20, entrances 21-23 and exits 4 and 25o

i Block 9 synchronization form the element OR 26, the counter 27, the builders 28-30, the counter 31, the element h 32, the element OR 33, the elements AND 34 | 35, the element IL 36, triggers 37-39 Element OR 40 and the generator 41 sync | pulse.

Frequency channel multiplexing is performed as follows.

From the input signals with the cutoff frequency F., which is related to the sampling frequency by the expression Fgjj / M, quadrature signal components are formed for each channel by multiplying the factors sin (2 r OTn Fc / 2) 31p {2 × GG) 5 cos (2 iv-bTn Fc / 2) cos ().

The filter works as follows

When a high level appears at the filter input 23, the sample counter 11 switches to the next state, the synchronization unit 9 generates the signals necessary for operation of the device, and the quadrature components are formed by multiplying the input samples by the sine and cosine values of the modulating function, which is performed in the following way. From the input 22 through the element: OR 10, the tracking pulse passes to the input of the 6 channel counter and transfers it to the next state, the code from the first output of the 6 channel counter goes to the first address input of the RAM block 1, to the address input of the 1B unit and element And 19, the first input of which receives a high level from input 23, to the second input of the second address adder 17, to the first input of which receives a signal c. output element EXCLUSIVE OR 20, the first input of which receives a high level from input 23, and its second input receives the value of the youngest of the bits from the output of the element And 19 (The second address adder 17 sequentially generates address codes that come to the input of block 16 memory from which the values of the cosine and sine of the modulating function are sequentially read and fed to the second input of the multiplier 3, the first input of which through the switch 14 from the input 21 of the filter receives the value of the input signal sampling The first input of the switch 14 receives the control code from the seventh output of the synchronization unit 9, as a result of which its first input is connected to the output of the switch 14.

In the first cycle of multiplying by the cosine of the modulating function, the result is recorded in the first half of the RAM block 1 at the address that is generated at the second address input by the first address adder 8 via block 7 under control of the signals from the sixth output of the synchronization block 9 In the second clock, the multiplied to the value of the sine of the modulating function, the result is written to the second half of the RAM 1 (the first / second half of the RAM 1 switches the pulse arriving at the control The first input of the block 1 of the RAM is from the sixth output of the synchronization unit 9 at the address formed at the second address input by the address adder 8.

With the arrival of the next tracking pulse at the input 22 of the filter

6 channel counter switches to. the next state and the processing of the information of the next channel takes place in the same way as described

After entering into block 1 of the operational memory, the values of quadrature components on all channels a high level from the input 23 of the filter is removed

with-

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processing the information read from block 1 as described.

After reading the N / L samples from the block 1 of the RAM and o6pia6oT-them, similarly to that described at the output of the accumulating adder 2, the predicted code is generated

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and the filter enters the interpolation mode of the sampling on the first channel at the third output of the counter 12 a pulse is generated, which is fed to the first input of the synchronization unit 9, which generates the third-party control signals.

The interpolation mode dp of each quadrature component of the signal is performed in the filter as follows. From the third output of block 9 syn-15 of its processing stage.

The clock is input to the input of the first counter 12; the first output of this counter is sequentially generated with the codes that arrive at the second input of the first address adder 8, the first input of which receives the code from the output of sample counter 11

In the first cycle, information from the RAM 1 is read at the address generated at the output of address adder 8, and is fed to the input of the second accumulating adder 2. During the second clock, the control input of block 7 receives the level of the logical unit from the third output of the first counter 12 and the information is read out from the 1. operative memory at the address converted by the block 7 and summed in the second accumulator 2o

After two read cycles, the output code of the second accumulating adder 2 through the second input of the switch 14 is fed to the first input of the multiplier 3, the second input of which receives the value of the filter impulse response coefficient. The address dp of reading the pulse-impulse response of the filter from the first block 5 of the permanent memory is received from the first output of the first counter 12. The result of the multiplication from the output of the y1 of the identical 3 is entered into the accumulating adder 4 by the pulses fed to its control input from the second output synchronization unit 9 Pulses from the first output of synchronization unit 9 are fed to the control input of accumulating adder 4 and zeroed it.

The first counter 12 switches to the next state, and during the next two clock cycles it runs

In the output of the counter 12, a pulse s is formed, which is fed to the first input of the synchronization unit 9, which generates the control signals third

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At the third stage, the fifth output Y9 of the synchronization unit 9, a controlled indi code dp switch 14 is formed, as a result of which its third input is connected to its output, the select signal of the second permanent memory block 16 is generated at the seventh output, a pulse that, through the element OR 10, transfers the counter of 6 channels to the next state and forms the recording channel in the address memory block 18.

The interpolated samples from the output of the accumulating adder. 4 through the third input of the switch 14 is fed to the first input of the multiplier 3, the second input of which receives the sine and cosine values of the modeling function from the fixed memory block 16 The address of the read out of the fixed memory block 16 is generated at the output of the second address adder. the second input of which enters through the element AND 19 code from the first output of the 6-channel counter, to the third input of the second address adder 17 receives information from the output of the address memory block 18, where the address code that was used during processing is stored the next sample is processed. The address code from the output of the second address adder 17 is fed to the input of the second constant memory block 16, after which this code is entered into the same cell of the address memory block 18 from which it was read

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From the output of the multiplier 3, the result of the multiplication is entered into the third accumulating adder 15, then the second quadratic component is processed as described above. As a result, the output of the accumulating sum is

topa 15 the first point of the Group signal of the frequency-impedance channels is formed.

Similarly to the described processing, the YTS and subsequent channels After the Q channels were processed, the filter switches to the standby mode until the next iero signal arrives at the input 23 of the filter. I The synchronization unit works as follows. At the first stage, processing 1CI pulse from the first input of the synchronization block 9 sets the second trigger 38 and the tracking impulse: the fourth input, synchronization block 9 sets the 370 trigger. The logical unit level from the output of the first trigger 37 forms the fifth output of the block 9- sync. the control code for the switch 14, using the OR element 26, generates I at the seventh output of synchronization unit 9, the selection signal dp of the second block: 16 permanent memory and using; OR element 40 allows the generator 41 to form a sequence |: clock pulses, . which, with the aid of the AND 35, forms on the sixth output of the synchronization unit 9 a write control signal to the operational memory block 1, and at the output of the OR element 36 a signal for selecting half of the operational memory 1 is generated, the first time of the first clock is selected

Golovin block 1 RAM.

bo The time of the second cycle is the second half, With an element. And 35 at (the output of the synchronization block Sf is the clock pulses dp of the first counter 12. After two counts (multiplied by the sine and cosine values of the modulating function), the one- to-third counter 31 resets the trigger 37.

After the first clock cycle, the result of decreasing by the sine value of the modulating function is recorded in the first half of the RAM 1 block, after the second clock cycle, the result of multiplying by the cosine value of the modulating function is entered into the second half of the RAM 1 block. the channel counter 6 goes to the next state and the described sequence is executed for the next channel. After processing all the channels with a pulse from the second input of the synchronization unit 9, the second trigger

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38 is reset and the synchronization unit 9 proceeds to generate control signals for the second processing step.

On the front of the pulses at the first input of the synchronization unit 9, a trigger 38 is set and the filter switches to interpolation mode, which is performed similarly to the prototype,

After the termination of the interpolation mode, the synchronization unit 9 begins to generate control signals dp of the third processing stage. Imdulse from the third input of the synchronization unit 9 sets the trigger 39, the logic level from the output of the trigger 38, the trailing edge transfers the one-bit counter 27 to the next state and generates the control code for the switch 14 on the fifth output of the synchronization unit 9 the counter 27 with the imaging unit 29 at the fourth output of the synchronization unit 9 forms a recording pulse for the unit 18.

The proposed device allows, in addition to interpolating input signals via Q channels, to generate a group Signal of frequency-compressed channels.

Claims (1)

Invention Formula A multichannel digital interpolating filter for frequency multiplexing of channels, containing a block of RAM, the output of which is connected to the first input of the first accumulating accumulator, a multiplier whose output is connected to the first input of the second accumulating adder, the output of which is the first output of the filter, synchronization unit, the first, second and third outputs of which are connected respectively with the second input of the second accumulating adder, the second input of the first accumulating adder and the input of the first account the first, second, and third outputs of which are connected respectively to the first input of the synchronization unit, the first input of the unit of the elements of the TORCHOCHA101ER or OR and the combined first inputs of the first permanent memory unit and the first address adder, the output of which is connected to the second input block of elements  TIPPING OR whose output is connected to the first input of the RAM, the sample counter, the input of which is combined with the third input of the synchronization unit and is the input of the filter operation mode, the output of the sample counter is connected to the second input of the first address adder, the OR element, which output connected to the input of the channel counter, the first and second outputs of which are connected respectively to the second input of the RAM and the second counter, the first and second outputs of which are connected respectively to The third input of the synchronization block and the second input of the first memory block, the output of which is connected to the first multiplier input, the fourth output of the synchronization block is connected to the first input of the OR element, the second input of which is a synchronizing input of the filter. filter application area due to the formation of the output group signal, a switch has been entered into it, a third accumulator adder, a second block of permanent memory, an address memory block, a second address adder, an AND element A CLOSE OR and an AND element, the first input of which is combined with the first input of the element EXCLUSIVE OR and connected to the input of the digital filter setting mode, the second input of the AND element is combined with the first input of the address memory block and connected to the first output of the channel counter, the output element I is connected to the first input of the second address adder and the second input of the element ELIMINATING OR, the output of which is connected to the second input of the second address adder, the output of which is connected to the first input of the second memory block and The first input of the memory block of the address, the output and the third input of which are connected respectively to the third input of the second v address adder and the fourth output of the synchronization block, the power input and the fifth output of the synchronization unit are connected respectively to the synchronizing input of the filter and the first input of the switch. dinene with the second input of the multiplier, the second and third inputs of the switch are connected to the outputs. Respectively of the first and second accumulating adders, the four-input input of the switch is an information input The sixth output of the synchronization unit is connected to the third input of the RAM and the first: input of the third accumulating adder, the second input of which is combined with the fourth input of the operational memory and connected to the multiplier output, the output of the third accumulating adder is the second output of the filter, The seventh output of the synchronization block is connected to the third input of the first block of permanent memory and the second input of the second block of permanent memory, the output of which is connected to the first input of the multiplier. FIG. 2