SU1524167A1 - Pulse train to square pulse converter - Google Patents

Abstract

The invention can be used in systems for processing and generating pulse signals. The purpose of the invention is to expand the functionality by ensuring the conversion of a series of pulses with a decreasing period of the sequence of pulses within the series. The Converter contains a generator 1 clock pulses, the driver 19, 20 pulses, triggers 2-4, valves 7-9 and counters 15, 16 pulses. The introduction of a pulse former 21, pulse counters 17, 18, a code comparison unit 22, triggers 5, 6, and gates 10-14 allows processing of a series of pulses not only with a constant period of pulse following within the series, but also if the period of pulse following decreases, with the excess of the subsequent period in comparison with the previous one being recorded as the end of the series. 2 Il.

Description

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The invention relates to a pulsed one and can be used in systems for processing and generating pulsed signals,

The purpose of the invention is to expand the functionality by providing a series conversion with a decreasing pulse period within the series.

In Fig.1, the electrical functional diagram of the converter is shown; 2 shows timing diagrams explaining the operation of the converter.

A pulse train to a square pulse converter contains a generator of 1 clock pulses, five flip-flops 2-6, eight gates 7-1A, four counters 15-18 and myles, three drivers 19-21 pulses, a block 22 of codes, an input 23 and two bus outlets 24 and 25, the input bus 23 is connected to the first inputs of the flip-flops 2 and 3, to the second input of the flip-flop 5 and through the pulse shaper 19 to the S-input of the Pulse Counter 18 and the first input of the valve 8, the second input of which is connected to the forward trigger output 5, and the output with a 1t generator control input assembly pulses, the output of which is connected to the C-input of the counter 15 pulses, the first inputs of valves 7 and 12 and the second input of the VENTIL 11, the output of which is connected to the C-input of the counter 18 pulses, and the first input - to the inverse output of the trigger 6, the second input of which is connected to the second input of the valve 10, the inverse output of the trigger 4 and the bus 24, the direct output to the first input of the valve 10, the control input of the code comparison unit 22 and the control input of the pulse counter 17, and the first input to the second trigger inputs 2 and 3 and the outlet of the valve 9, the first input is The second input is connected to the output. The transfer of the counter is 16 pulses, and the second input is connected to the output. The transfer of the counter is 15 pulses, the S input of which is connected to the output of the valve 13, and the control input to the input of the generator of 21 pulses and the inverse output of trigger 3 the output of which is connected to the input of the pulse driver 20 and the control input of the pulse counter 16, the S input of which is connected to the output of the valve 14, and

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The C input is with the output of the valve 7, the second input of which is connected to the second input of the valve 14 and the direct output of the trigger 4, the first input of which is connected to the first input of the valve 14 and the output of the pulse forming device 20, and the second input to the first input of the trigger 5 The S-input of the pulse counter 17 and the output of the block 22 of the codes, the first and second groups of inputs of which are connected to the corresponding outputs of the counters 17 and 18 of the pulses, the C-input of the pulse counter 17 of the pulses is connected to the output of the valve 12, the second input of which is connected to the output of the valve 10 control input Meters withstand pulses 18 is connected to the common bus, the flip-flop inverse output 2 is connected to the bus 25, and the forward output - to the first input gate 13, a second input coupled to an output of the pulse shaper 21.

The Converter operates as follows.

In the initial state, the reversible pulse counters 15-18 are installed in a single state (all sections are filled). At the overflow outputs of these pulse counters - a low level of activity, at parallel outputs - high. Counting trigger 3, as well as triggers 4-6 are set to zero, with which at their direct outputs - low potential, and at inverse ones - high. The outputs of the formers 19–21 pulses — high potential. The generator of 1 clock pulses is in a decelerated state due to the presence of a low potential at its control input. Suppose that reversible counters work on subtraction in the presence of the first potential at their control inputs. V, and addition, if there is a high potential at their control inputs

Shapers 19–21 pulses are triggered by a change in potential at their inputs from high to low and form a short pulse of low activity at the output. Counter 18 is subtractive.

When a negative pulse arrives at the S inputs of the counters, they are set to the initial (filled) state of the Code Comparison Unit 22 when the code on the first inputs A coincides with the code on the second inputs B and

at a high level at the control input, V generates a short impulse at its output. Trigger 3 operates in the counting mode. The oscillator 1 of clock pulses at a high level at its input generates square clock pulses. He is locked at a low level of potential for his needs, in this case there is a low level of potential at his exit.

When the first impulse of the series (Fig. 2a) arrives at the input bus 23, the triggers 3 (Fig. 26), 5 (Fig. 2b) and 2 are set to ONANAN, the pulse shaper 19 is started (Fig. 2d) which produces a low-low pulse that maintains a low potential at the outlet of the valve 8 and confirms the initial (filled) state of the counter 18.

The pulse duration of the low level of the pulse generator driver 19 is selected with a slightly longer transient time in the converter and a shorter pulse period of the reference frequency. When Trigger 3 is set to one, a high potential appears at its forward output, low. In this case, the subtraction mode is set in the reversible counter 15, and the addition mode is set in the reversible counter 16.

When trigger 5 is set to a single state, a high pickup appears at its direct output (Fig. 2B); when trigger 2 is set to a single state, a high potential is set at its forward output, and low at its inverse output ( figure 2) about

Consequently, a front edge of a rectangular pulse appears on the converter bus 25, which coincides with the moment of arrival of the first pulse of the series. Trigger 4 continues to remain. c in the zero state (fig, 2d), and the low potential from its direct output keeps the valve 7 in the closed state of the pin (fig. 2i). At the same time, a high potential remains on the bus 24 (FIG. 2) At the end of the pulse from the pulse generator 19 (FIG 2 d), the clock pulse generator 1 begins to generate pulses (FIG. 2h), which through gate 1 1 act on the counter 18.

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The counter 16 continues to remain in the initial state, since the reference frequency pulses do not arrive at its C input (Fig. 2i). Counter 15 operates on the subtraction before the arrival of the second pulse of the series. At the same time, clock pulses through gates 12 and 11 arrive at the C input of the roar (iridescent counter 17 (fig.2k) I counter 10, y :: c}; their contents

When the second pulse of the series arrives, trigger 3 is set to a bullet state (FIG. 2b), a low thermal appears in the control input of counter 16 (subtraction mode), and a high potential is added to the control input V of counter 15 . Changing the potential from high to low at the direct output of trigger 3 triggers a pulse generator 20, the output negative pulse of which (fig2c) sets trigger 4 to one state, allowing the pulses to pass through valve 7

The pulse from the pulse shaper 19 is fed to the S-input of the counter 18 and sets it to the initial (filled) state. A negative pulse with a forcing 20 pulses through the valve 14 is fed to the S input of the counter 16 and confirms its initial filled state

Low levels at the inverse output of the trigger 4 and at the direct output of the trigger 6 lead to the prohibition of the passage of clock pulses through the valve 12 to the reversible counter 17 (Fig. 2k)

With the appearance of a low level of activity on the inverse output of trigger 4 on the bus of FIG. 2), the leading edge of a pulse delayed by time G, appears,

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With the arrival of the second impulse of the series

On the reversible counter 17, the code corresponding to the time between the first and second pulse begins to be stored. With the arrival of each new pulse of the series on the input bus 23 (FIG. 2a), the counter 18 is reset and counts the length of the period of each pulse of the series. . On tires 24 and 25 pulses are formed, one of which is delayed by time, r- in the period of the first impulse of the series, and the other coincides with its leading edge

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home of the first impulse of the series. Now the reversible counter 15 works on addition, and the counter 16 - on subtraction.

With the arrival of the third pulse of the series, the trigger 3 changes the operation mode of the reversible counters 15 and 16, the counter 18 is reset.

At the moment of arrival of the next pulse of the series, the operation mode of the counters 15 and 16 changes. If the counter worked on addition, it will work on subtraction, and vice versa (due to a change in the state of the trigger outputs 3).

If the next pulse of the series does not arrive at the input bus 23 of the converter, i.e. T, c ;, then the clock pulse generator is not blocked and its regular pulse, arriving at the C inputs of both counters 15 and 16, causes an overflow of that reversible counter, which at this time worked on addition and turned out to be filled. The counter overflow pulse through valve 9 (Fig. 2l) returns the triggers 3 and 8 to the initial (zero) state and cocks the trigger 6 (Fig. 2m), which permits operation of the code comparison unit 22

When trigger 2 is set to its initial state, a low level of activity appears on its direct output, setting counter 15 to its initial state, and a high potential at the inverse output, indicating the end of the sequence (Fig. 2),

The high potential at the direct output of the trigger 6 () through the valve 10 allows the passage of clock pulses to the input of the reversible counter 17 (Fig. 2k).

The low potential of the inverse output of the trigger 6 prohibits the passage of clock pulses to the input of the counter 18, the high potential of its direct output switches the reversible counter 17 to the add mode. At this moment, the counter 18 has the number of the corresponding time between the last and next to last pulses and on the reversible counter 17, the code corresponding to the time between the first and second pulses of the series. Now the contents of the reversible counter 1 7 begins to increase with and, as soon as the reversing account

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17 and the counter 18, the codes will become identical 91, the code comparison block 22 generates a pulse (fig.2n) with a duration sufficient to reset the flip-flops 5 and 4, as well as the reversing counter 17 to the initial state

The inverse output of the trigger 4 on the bus 24 (FIG. 2) marks the end of a pulse shifted by an amount equal to the duration of the pulse train.

Thus, on bus 24, a rectangular pulse equal in duration to a series of pulses at the input and delayed by the value, was obtained. ,

On bus 25 (FIG. 2), a pulse was received, the beginning of which coincides with the arrival of the first pulse of the series, and the ending is delayed relative to the series spin by the value of the period of the last pulse () ,.

Claims (1)

Invention Formula A pulse train to a square pulse, containing clock generator, the output of which is connected to the C-input of the first pulse counter and the first input of the first valve, and the control input - to the output of the second valve, the first input of which is connected to the output of the first pulse shaper, the input of which is connected to the input bus and the nepBbrNm inputs of the first and the second trigger, the second input of the last of which is connected to the output of the third valve and the second input of the first trigger, the inverse output to the control input of the first pulse counter, and the direct output to the control input of the second pulse counter and through the second pulse shaper - to the first input of the third trigger, the inverse output of which is connected to the first output bus, and the direct output to the second input of the first valve, the output of which is connected to the C input of the second pulse counter, the output of which is connected to the first input of the third valve, the second input of which is connected to the output of the first pulse counter, the inverse output of the first trigger is connected to the second output bus, which, in order to expand  functional possibilities due to 9- provide a series of pulses with a decreasing follow-up period, the third and fourth pulse counters, a code comparison unit, a third pulse shaper, fourth and fifth triggers, and five gates, with the second input of the third trigger connected to the first input of the fourth trigger, S- the input of the third pulse counter and the output of the code comparison unit, the first and second groups of information inputs of which are connected to the corresponding outputs of the third and fourth pulse counters, and the control input is connected to the first input of the fourth valve, the control input of the third pulse counter, the direct output of the fifth trigger, the first input of which is connected to the output of the third valve, the second input to the first output bus and the second input of the fourth valve, and the inverse output to the first input of the fifth valve whose output is connected to the C-input of the fourth pulse counter, and the second input 67 ten with the output of the clock pulse generator — with the C input of the first pulse counter and the first input of the sixth valve, the output of which is connected to the C input of the third pulse counter; and the second input with the output of the fourth valve, the control input of the fourth pulse counter is connected to the logic zero bus and the S input is with the first input of the second valve, the second input of which is connected to the output of the fourth trigger, the second input of which is connected to the first input of the second trigger, the direct output of which is connected to the first input of the seventh valve the stroke of which is connected to the S-input of the first pulse counter, and the second input to the output of the third pulse generator, whose input is connected to the inverse output of the second trigger, the output of the eighth valve is connected to the S-input of the second pulse counter, the first input - to the output of the second pulse shaper , and the second input - with the direct output of the third trigger. .eleven JlIshIlShlshul lllshushshshlShl