SU1524060A1 - Device for interfacing computer with fax machine - Google Patents

Abstract

The invention relates to computing and can be used in automated high-performance complexes of receiving and transmitting and processing facsimile information. The purpose of the invention is to expand the class of tasks performed by the device by providing data buffering, as well as eliminating tight synchronization between the moments when the information enters the input register and is read by the central process. To do this, a device buffering information consisting of two switches is inserted into the device containing the transceiver unit, interrupt unit, address decoder, multiplexer 4, interrupt vector address storage unit, device selection trigger, control signal decoding unit, and status register 8. two storage nodes, a decryption node, a synchronization node, a clock generator, and a data register. The device has two modes of operation - reading information from a fax machine into a computer memory and outputting it from a computer memory to a fax machine. 5 il.

Description

35 dat-jq pulse counter - for sampling not

sa and memory element 36, the second switchboard (multiplexer) 37, decryption node 38, second storage node B, consisting of an address counter 39 and memory element 40, data register 4, time, 42 clock pulses, synchronization node 43, intrablock links 44-55.

Node 43 synchronization contains

The black-and-white without halftones, the facsimile image signal is discrete in amplitude and continuous in element duration.

(FIG. 3) the thrigger 56, the AND-HE element 57.49 of which it consists. For the input of the trigger data 58, the counter 59, the elements AND 60-62, the element OR 63, the element AND-NOT 64, the trigger 65, l

Node 38 decryption contains (Fig, 4) the element And 66, the element OR 67, the elements 5 FA. To the black image element of the sleep signal in the computer, it is discrete in the interface device in time with an error determined by the resolution

And 68 and 69, the element OR 70, the element And 71, the element OR 72, the element NOT 73, the element AND 74, the element OR 75, the elements AND 76 and 77, the element OR 78, the element AND 79, the element 80 and the element YPI 81 ,

Interrupt block 2 contains (FIG. 5) element AND 82, trigger 83, element OR 84, trigger 85, element AND 86, element HE 87, trigger 88, element OR 89, triggers 90 and 91, element 92 and trigger Ger 93 ,

Information buffering unit 9 allows conversion and input of information from facsimile terminal 55

corresponds to logical 1, to white - O. Image input is performed line by line, data is synchronized using the end of line (CS) signal generated by the FA,

The device has two modes of operation: Input - read information from the FA to the computer memory and Output - write information from the computer memory to the FA,

In the information reading mode (Input), the control signal on line 31 from the state register 8 is fed to the inputs of nodes 34, 38 and 43 (FIG. 2) and

time-discontinuous signal with FA and for shifting information in the data register 41.

The device works in the following manner.

The black-and-white without halftones, the facsimile image signal is discrete in amplitude and continuous in element duration.

of which it is composed. To enter a data

F. To the black image element of the sleep signal in the computer, it is discrete in the interface device in time with an error determined by the resolution

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corresponds to logical 1, to white - O. Image input is performed line by line, data is synchronized using the end of line (CS) signal generated by the FA,

The device has two modes of operation: Input - read information from the FA to the computer memory and Output - write information from the computer memory to the FA,

In the information reading mode (Input), the control signal on line 31 from the state register 8 is fed to the inputs of nodes 34, 38 and 43 (FIG. 2) and

switches the operating mode of the device. The signal level, corresponding to the Input mode, is fed to the control input of multiplexer 34, commuting to the line 45 a signal from the photoelectric converter of the FA from line 32. The initialization of the logic operation is carried out by the control signal from the line of the FA from the line 21, Active level on this line, resets the address counters 35 and 39 and the initial installation of the sequence building unit 43, and also entering interrupt unit 2 initiates an interruption request for software synchronization of the device and the computer CPU.

At the signal of the COP node. 38 switches the operating modes of the counters 36 and 39 and the memory elements 36 and 40: one pair is prepared to record information from the FA, the other at the same time reads the information recorded from the FA at the previous clock cycle. The distribution of control signals between the nodes is carried out on lines 48-51 in accordance with the signal level on line 52 from node 43, the same signal switches to output 33 of multiplexer 37 that memory element output from which the reading is performed in this cycle. information in the computer memory,

Consider the operation of logic for the case of collecting information by node A and reading information from node B,

The analog signal from the FA arriving on line 32 is gated with the frequency generated by generator 42 on line 53. By removing the active level on line 21, i.e., at the beginning of the sweep of the image line, node 38 passes a signal from output 49 line 53 and thereby writing the code from line 45 to memory element 36; At the moment of removing the active level on line 49, line 48 is activated, increasing by one the contents of counter 35, and the next cell is selected for writing the code. Then the cycle is repeated.

Thus, the analog signal from line 32 is sampled over time and recorded into memory element 36 (40). The capacity of a one-bit memory element is selected based on the sampling rate; it should not be less than the number of samples in one line of the image. Next signal arrival

The CS, which winds up the scanning process of a single image line, results in the removal of recording pulses on line 49, and the node A switches to information storage mode.

Reading information from the memory and converting it into a parallel code necessary for data exchange with a computer through a parallel interface, consider the example of the operation of the node B.

To generate control signals for reading and converting information, the clock frequency generated by generator 42 on line 54 is used. By removing the signal from the CS, the logic for generating the sequence of node 43 is triggered. The signal of output line 52 of node 43 performs switching through memory multiplexer 37 of memory element 40 To the serial input 33 of the register 41, Thus, at the input of the shift register are data recorded at the zero address in the memory element 40. Then, the node 43 begins to produce shear pulses, which also come from the line 55 to the input of the node 38 and are fed through the output line 51 to the counting input of the counter 39. On the line 50, the level prohibiting writing. information in the memory element 40, t, e, the latter is switched to the information storage mode. Each active level on line 54 increments the content of counter 39 and shifts the contents of memory element 40 received at this address into register 41. The shift sequence is generated by node 43 by whether or not 55

The number of pulses on this line is determined by the register width. After the register 41 is full, the node 43 stops the pulse sequence on line 55 and generates the active level on line 20, which enters block 2 interrupts and confirms that data is available on the parallel output 25 of register 41. At the same time, block 2 generates an interrupt request signal line I3 and switches the signal on control line 18 multiplexer 4 to transmit to block 1 transceivers via bus 26 the interrupt code from block 5, the computer accesses the device in the Input cycle and reads the code of interrupt vector through bus 12 confirming that the interrupt cycle is performed by the active level on line 1A. After this, block 2 removes the switching signal of multiplexer 4 on line 18. Thus, the processor interrupt cycle ends and the latter is programmatically transferred to the data transfer mode from the device. This completes the next cycle.

The processor places on the information bus 12 the address of the device, which is received by block 1 and through the output of the 1st 16, enters the decoder 3 of the address. The latter generates an active level at the output, which is transmitted to the information input of the trigger 6 for the selection of the device. Accompanying & irabota1 address code synchronizes the signal on line 1 1 gates data in. the trigger 6, thereby at its output 21, the active level is formed. Wherein. ciirHan from the synchronization line 1 1 also goes to block 7 and an active level appears on its output line 10, signaling the completion of the address cycle. After that, it generates the active level on line 23, switching multiplexer 4 to transfer data from the bus 25, which is connected to the output group of the parallel register code A1, and the signal on line 15 switches unit 1 to transfer information from bus 17 to bus 12,

Thus, the parallel code from register 41 through multiplexer 4 and transceiver unit 1 enters the computer channel. When executing a data reading cycle, i, e, after removing the active level on line 11, unit 7 generates a signal on line 28 confirming the completion of the input information - in the computer and triggering the logic of block 9 to read the next word from the memory element 40 (36) of the next word a. After all the information stored in the buffer memory has been read, the central processor accesses the device at the address corresponding to the address 8 of the device status register. In this case, block 7 generates on line 30 a signal strobe in register 8 an interrupt masking code, which enters via line 19 to block 2 and prohibits the generation of an interrupt request on line 13. At the same time, node 43 stops the generation of shift pulses, since it does not receive read confirmation signal on line 28, t, e, the number of words read is controlled by the computer,

In the mode of displaying information from .PAM computer on the FA device works as follows

Switching to this mode is carried out by recording in the state register 8 a code corresponding to the active state on line 31. In this case, the multiplexer switches the output signal from the serial output of the register 41 to the output line 45. A feature of the node 43 in this mode is that the signal to line 20 must be generated before the shift pulse on line 55 is obtained. This ensures that the required information is stored at the lower addresses of the memory element, that is, first, the data is strobed from the computer memory to the data register 41, and then the shift vyi pulses recorded in the memory device. For this, the signal from line 31 enters node 43 and organizes the latter so that the signal on line 20 is generated immediately after removing the active level on line 21. Next, a processor interrupt cycle is performed in the same way as described for Input, After This processor performs information output to the device by accessing it at the input register address. In this case, unit 7 generates a signal on line 15 that switches unit 1 to receive information from bus 12 to bus 16, and data from the computer is sent to a group of inputs of parallel loading of register 41. After that, output 29 of block 7 shows the active level strobe the data in the register and starts the node 43 to produce shear pulses.

The level from line 31 arriving at node 38 distributes the control signals so that the write enable signal on line 49 and the increase in the contents of counter 35 of address on line 48 are generated from shift pulses on line 55, which is stored in memory element 36 information from register 4 1,

Consider outputting an image line from the device buffer memory to I -,

fax machine.

A level that prohibits writing to memory element 40, t, e, is applied to the arm participating in the output of information from node 38; signal on line 50 is passive for arm B. The signal on line 51 is formed from clock pulses on

the output 53 of the generator 42. The signal from the line 52 is then transmitted through the multiplexer 37 to the output line 33 connected to the recording amplifier of the FA, the output code from the line 47, i.e. The output of data from the buffer memory is performed with the same frequency as the reading of information from the FA in the Input mode, which ensures accurate image output.

Switching nodes A and B is performed by a signal from line 52 at the time of the appearance of the active level on line 21 End of construction. Both nodes are equal, the initial choice is arbitrary and not specifically made.

The operation of the node 43 (FIG. 3) is carried out as follows.

In the case of Input mode, line 31 is fed from a register low. This level sets the trigger 58 to unity, while the high level from the output of the trigger 38 is applied to the input of the element And 61, allowing the output signal from the overflow output of the counter 59 to be passed to its output. The active signal on the line 21 is high. Therefore, the arrival of the signal. The end of the line on this line causes the counter 59 and the trigger 63 to be reset. Trigger 56 is enabled in the counting mode. The arrival of the active level causes the trigger to switch, and a signal is generated at its output, coming through line 52 to node 38 and switching nodes A and B. Unlocking a high level on line 21 triggers the start of logic. The pulses from the generator 42 through line 54 arrive at the counting input of the counter 59 and through the signal 62 opened by the signal of the inverse output of the trigger 65 And 62 - on the line 55.

After sixteen pulses are formed, the counter overflow output is a negative pulse that arrives at the input of the OR 64 element and switches the trigger 65 with its falling edge. In this case, an active high level is formed on line 20, i.e. interrupt request set. The same level prohibits the passage of 63 clock pulses from line 54 through the iUIH element, while the inverse level blocks AND 62, the arrival of the data read confirmation signal from block 7, flips trigger 65 through line 28, i.e. the clock counting process is repeated.

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In the case of the mode of displaying information on the FA, the logic of the node 43 operates as follows.

From the 8 state register, line 31 is fed high. This level opens the element And 57, sets the unit at the information input of the trigger 58, opens the element And 60. Signal arrival The end of the line on line 21 resets the counter 59 and the trigger 66, as in the Input mode and, moreover, through the element And 60 and the element OR-NA 64 trailing front records the unit, i.e. an interrupt request signal is immediately generated on line 20. After the processor completes the interrupt and, setting information to the data register 41, generates a confirmation signal on line 29, the trigger 65 changes its state again and allows the formation of shear pulses. In addition, the unit 58 is recorded in the trigger 58, the element And 61 is opened, and then the process of generation of shear pulses proceeds as in the case of the device operation in the Input mode.

Node 38 operates as follows (Fig. 4),

The signal on line 31 from state register 8 determines the logic operation mode: Input or Output. In the case of Input mode, the low level on line 31 blocks the passage of signals to the outputs of elements H 68 and 67 and ,. Passing the element 73, opens elements 66 and 74. The low level of the signal on line 52 corresponds to the choice of the node A for collecting information from the FA and the node B for reading data into the computer memory.

The flow of signals to the output lines in this case is carried out as follows.

The signal for gating information from the generator 42 clock pulses on line 53 enters the inputs of elements AND 66 and 76. Since element 76 is closed by a low level on line 31, the clock pulses pass only at the output of element AND 66 and through element OR 67, on the second level the input of which is low from the closed element And 68, arrive at the inputs of the elements And

69 and 71. The inverted level on line 52 allows the signal to pass through the output of the element AND 69, from where the signal hits the inputs of the elements OR

70 and 78. Since the first input of the element OR 70 is low, then

its output is passed through pulses permitting zaggsh to the element 36 of the memory. Similarly, pulses pass to the output of the element OR 78, since at its second output a low level from the closed element AND 77, For shoulder B, the control levels are formed as follows. The sequence of shear pulses from node 43 via line 55 enters the inputs of And 68 and 74 elements. Since And 68 closes a low level on line 31, shear pulses pass only through And 74, then through ShSh 75, at the second input of which the low level from the closed element AND 76, arrives at the inputs of the elements AND 77 and 79, Since only the element AND 79 is open, the pulses pass to the input of the element OR 81, at the second input which is low from the closed element AND 71, the write enable signal in memory element 40 in this case should passive, which is achieved by feeding the second input element OR 72 a high level,

In the Input mode, control signals are generated as follows.

IN LIST, 31 is fed high. It opens the elements of And 68 and 76, and closes the elements of And 66 and 74, Shifted on line 55, passes through the open element And 68, moves to the second input of the element OR 67 and, since the first input of this element is low from the closed element And 66, goes to the output and is fed to the inputs of the elements And 69 and 71, Opened in the case of a low level on line 52, only the element And 69, From its output, the signal goes to the elements OR 70 and 78, Since the first input of the element 70 is low level, the pulses go to write write permission line 49 in memory element 36. Similarly, the shift pulses are passed to the increase line 48 of the contents of the address 35 counter. For arm B, the increase control of the contents of the counter 39 is generated from the pulses along the line 53 through the elements AND 76, OR 75 and 81, The signal on the write resolution 50 is passive, because the element OR 72 is closed by a unit from the output of the inverter 80,

Interrupt unit 2 (FIG. 5) operates as follows.

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The interrupt generation control from line 20 is carried out by And 82 and 86 elements and triggers 83, 85 and 88, from Line 21 by And 92 elements and 90, 91 and 93 triggers,

In the case of a request for an interrupt on line 20, a signal from the state register 8 on line 18 controls the resolution of the interrupt. In the case of a high Level on this line, the requirement passes to the input of the setting in the trigger unit

83, the direct output of the trigger 83 through the OR element 84 generates on line 13 a signal for interrupting a channel in a computer channel. When the central processor is ready to service the device, it generates an interrupt signal on line 14. In this case, a unit is recorded in the trigger 85, since at its information input there is a high level from the set trigger 83,

The provision of interrupt and high is dropped from the output of the trigger 85 through the element 86 and through the element OR 89 forms a signal on line 18, which enters multiplexer 4 and switches the code from its block from the block 5 to form the address of the interrupt vector. In addition, I signal from the output of the element And 86 the trigger 83 is reset, the casfciM removes the demand on line 13. After the processor completes the program interruption cycle, it removes a high level from line 14, the trigger 88 is set by a signal from the output of the element HE 87 and resets the trigger 85, is set infusing logic unit 2 to its initial state.

The operation of the second direction of the block is identical to that described, but differs by the absence of an interrupt masking mechanism and the presence of a line 22, which arrives at block 5 and serves to change the address code.

Claims (1)

Invention Formula A computer interface with a fax machine, containing a transceiver unit whose input-output is the input-output of the device for connecting to a computer address data bus, and a control input connected to the first output of the decoding unit of control signals, the second output and the synchronous input of which is the corresponding output and input of the device for connecting to the blue output of the computer, input-typing, first and formation inputs of which are connected respectively to the output register groups of the state register and interrupt vector address block, the start input of the interrupt block connected to the first output, the second output and the enable input of which are the corresponding output and device input for connecting to the interrupt request input and interrupt enable output The computer, and the third output and the first interrupt request input are connected respectively to the first control input of the multiplexer and the first bit output of the register No, the control input of the control signals connected to the third output of the decryption block, the third output and the enable input of which are connected respectively to the second control input of the multiplexer and the output of the device selection trigger, the output of the multiplexer is connected to the information input of the transceiver unit whose output is connected to the information inputs of the register the state, the decryption block of the control signals and through the address decoder with the information input of the device selection trigger, the synchronous input of which is It is connected to the input of a device for connecting to a synchronization output of a computer, characterized in that, in order to expand the class of tasks of the device by providing buffering of analog signals from a fax machine, an information buffering block is inserted into it, including a data register, a synchronization node, a clock generator pulses, two storage nodes, two switches and a decryption node. the first information input of the control and the clock input of the register of the dan switch and the output of the second com-unit, the permitting input of which of the submutator are the corresponding keys to the fifth output of the block, the decoder input and the output of the device for the sub-c and control signals, the keys to the information output and five 0 ABOUT five 0 five the first and second information inputs of the second switch are connected respectively to the outputs of the first and second storage nodes, and the control input and output are correspondingly with the first output of the synchronization node and the input of the serial data register code, the information input and output of the parallel code of which are connected respectively with the output of the transceiver unit and the third group of information inputs of the multiplexer, the output of the serial data register code is connected to the second information the first input of the first switch, the output connected to the information inputs of the first and second storage nodes, and the control (with the second bit output of the status register, the mode input of the synchronization node and the first information input of the decryption node, the first to fourth outputs of which are connected respectively to the synchronizing and enabling inputs of the first and second storage nodes, the reset inputs of which are connected to the input of the initial installation of the synchronization node and are the input of the device for connecting to synchronizing output of the facsimile apparatus, the second and third information inputs and the sync input of the decryption node are connected respectively to the first and second outputs of the synchronization node and the first output of the clock generator, the second output connected to the clock input of the synchronization node, the start and block inputs, the third and second. 1, respectively, with the fifth and sixth outputs of the decoding unit of the controlled signals, the second input of the interrupt request of the interrupt unit. g Phie. five figure 1