SU1327115A1 - Apparatus for mating a group of subscribers to a communication channel - Google Patents

Abstract

The invention relates to computing technology, in particular, to information transmission means, and can be used in control systems of a wide purpose for organizing operational data exchange between subscribers and a computer. The aim of the invention is to increase the speed of the device by organizing the packet transmission of messages from subscribers and consequently reducing the unit cost of transmitting one message. The device contains a group of 1 buffer registers, a group of 2 reversible counters, a register of 3.4 shift, a group of 5 registers, a group of 6 comparison elements, elements OR 7,8,9, 10 delay elements. I il, S

Description

The invention relates to computer technology, in particular, to the transmission of information, and can be used in control systems of a wide purpose for the organization of operational data exchange between information sources and computers.

The aim of the invention is to increase the speed of the device by organizing packet messages from subscribers and reducing

consequently, the unit cost of time for transmitting one message.

The drawing shows a diagram of the device.

The device contains a group of 1 buffer registers, a group of 2 reversible counters, 3 and A shift registers, rpyjjny 5 registers, a group of 6 comparison elements, OR 7 9 elements, a delay element 10.

The device works as follows.

The message to be transmitted is initially fed to the information input of the corresponding buffer register 3. The recording of the message

Register 1 is carried out by the clock signal aWf received from the device clock input and the write signal. The recording signal is fed simultaneously to the input of the register 1 and the summing input of the reversible counter 2, with the result that its content is increased by one.

Reading information from registers 1 is carried out by packets of K (K 1) messages on the read signal coming from the output of the corresponding comparison element 6. At the same time, the read pulse is fed to the subtracting input of the reversible counter 2, as a result of which its content decreases by K units. Thus, the contents of counter 2 correspond to the length of the queue of messages waiting to be transmitted.

The reading of the contents of the reversible counters 2 into the corresponding registers 5 is effected by the read signals from the corresponding outputs of the shift register 3. The operation of register 3 occurs under the influence of the clock signals coming from the synchronous input of the device. Under the influence of the clock signals, a read pulse (logical unit)

five

0

sequentially moves from one bit of register 3 to another and after passing the last younger bit enters the sradkky bit. The pulse from the output of the high bit of register 3 enters through the element OR 9 to the synchronous input of another register 4 to initiate its operation,

From register 5, a digital service message corresponding to the length of the current message queue in the corresponding lean register 1 is read into the corresponding comparison element 6. Comparison element 6 compares the length M of the corresponding queue with a threshold equal to the number of K messages in the group. If MK, then from the first output of the comparison element 6 a logical unit is fed to the read input of the corresponding buffer register 1 and the subtracting input of the reversible counter 2, as well as through the OR elements 7 and 9 and the 5 element 50 of the synchronous input of the register 4 element 10 is equal to H + CT, where K is the number of messages in the packet; T is the time of transmission of one message} N is the time spent on the transmission of the packet. The elements OR 7-9 serve for the purpose of untiing a chain-service,

As a result of the signal input to the synchronization register A, it is initiated, its next output is compared with the content threshold of the next register 5, This continues until the last bit of register 4 is initiated, from which the pulse (logical unit) is fed to the input of register 3 and is recorded in its first bit (at the initial moment of the device operation, the first digit of the register 3 is recorded from the input of the initial device setup),

We begin a new cycle of polling the counters 2 and recording their contents in registers 5,

If, then from the second input of the comparison element 6 the pulse goes through the elements OR 8 and 9 to the synchronization register 4 and initiates its next output

Thus, the device implements periodic polling of the contents of reversible counters, automatic selection of those buffer registers whose queue length exceeds the threshold K, and transmission of a packet of messages from them.

five

0

five

0

five

313

In this case, the cycles of polling the contents of the counters and the cycles of data transmission from the buffer registers alternate,

Claims (1)

Invention Formula A device for interfacing a subscriber group with a communication channel, containing a group of buffer registers, a group of comparison elements and a delay element, the outputs of the buffer registers of the group forming the output of the device for connecting to the communication channel, the information inputs of the buffer registers of the group for connecting to the information outputs of the respective subscribers of the group, characterized in that, in order to increase speed, two shift registers are entered into it, a group of registers, a group of reverse accounts three OR elements, while the write entries of the buffer registers of the group form a group of inputs of the device to connect to the outputs of the group subscribers and are connected to the inputs of the account increase control of the corresponding reversible counters of the group, the sync input of the first shift register is connected and is the synchronous input device, the installation input of the first shift register is the input of the initial compiler C, Pestmal Editor L. Veselovska Tehred I.Popovich Proofreader G. Reshetnik Order 3391/46 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, st. Project, 4 15 The device setup, the synchronous inputs of the reversible counters of the group are connected to the group of lower bits of the output of the first shift register, the output of the high bit of which is connected to the first input of the first element OR, the output of which is connected to the synchronous input of the second shift register, the output of the high bit of which is connected to the recording inputs of the first and the second shift register, the group of the lower bits of the information output of the second shift register is connected to the write inputs of the corresponding group registers, the information inputs of which are DINENA with the outputs of the corresponding reversible group counters, the counting control inputs of which are connected to the counters of the corresponding buffer registers of the group, with the outputs Equivalent to the corresponding comparison elements of the group and with the corresponding inputs of the second OR element whose output is connected to the input of the delay element whose output is connected with the second input of the first element OR, the third input of which is connected to the output of the third element OR, whose inputs are connected to the outputs of the Unequally corresponding lementov comparator group whose inputs are connected to outputs of the respective registers of the group.