SU1603392A1 - Computer to telegraph line interface - Google Patents

Abstract

The invention relates to computing, in particular, to interface devices, and can be used in remote data processing systems. The purpose of the invention is to increase labor productivity by processing information that arrives simultaneously through several channels. The device contains a control unit, a channel counter, a switch, a parcel polarity decoder, a reversible counter, two comparison blocks, a constant register, a parcel counter, a multiplexer, a shift register, a buffer register. A device for interfacing telegraph lines with a digital computer using the digital integration method in the interval between two gating pulses of parcels sequentially processes the information coming through the channels. The processing of information on each channel consists of reading tuning words from arrays M1 and M2, counting gating pulses and the number of received parcels, analyzing the states of impulse counters and parcels on comparison circuits, issuing the generated impulse count, counter parcels, reversible counter and shift register in the array M2 of the memory and adding one to the channel counter. 4 il.

Description

The invention relates to computing, in particular, to interface devices, and can be used in remote data processing systems.

The purpose of the invention is to increase the productivity and utilization of equipment by processing information that is received simultaneously via several (n) channels.

Figure 1 shows the structural diagram of the device; Fig. 2 is a block diagram of the control unit; in FIG. a diagram of the connection of the device with the operational memory and the main-computer main circuit; figure 4 is a temporary diagram of the operation of the device.

A device for interfacing telegraph lines with a digital computer contains a clock input of 1 device, a signal input 2, a control unit 3, an input

31

4 start1, .installation ,, in 5 channels, counter 6 channels, switch 7, descrambler 8 and parcel, reversible counter 9, pulse counter 10, unit 11 comparison, regis 12 constants, unit 13 comparison, counter 14 parcels ,, multiplexer 1 shift register 16, buffer register 17, device signal output 18, information output 19 devices output mode 20, request output 21, output 22 of the high-order address, address outputs 23 devices / 1 information inputs 24., II information inputs 25, I, II, III and IV information outputs 26-29, IV and III information inputs s 30 and 31 respectively.

In figure 1 indicated: 32 - the output of the switch 7; 33 and 34 - summing and subtracting the inputs of the reversible counter 9, respectively; 35 output of high-order reversing counter 9; 36 - output of the lower section of the shift register 16; 37 - input recording information on the register 12 constants; 38 - counting input of the counter 10 pulses; 39 — enable recording of the current state of the counters 9, 10, and the shift register 16; 40 - reset the counter 10 pulses; 41 - permission to write the counter of 14 parcels; 42 - counting input counter 14 parcels; 43 least significant bit of the I group of information inputs of the multiplexer 15; 44 - reset the reversible counter 9; 45 - counting input of the counter 6 number of channels; 46 - output sign of the bipolar parcel from the register of 12 constants; 47 is the output I of the comparison circuit 11; 48-1 group of information inputs of the multiplexer 15; 49 - information inputs of the counter 14 parcels.

The control unit (figl) contains a 50 clock counter, a decoder 51 elements OR 52, a trigger 53, elements AND 54-60, the most significant bit of the counter 61 pulses, element AND 62; element OR 63J elements AND 64 and 65j elements OR 66 and 67, element AND 68,

I

FIG. 2 denotes 69 and 70 — outputs of the decoder 51; 71 - the output of the element And 60; 72 - installation input

1 high pulse counter; 73 - output of the element 62; 7 - output element OR 67 j 75 - output element And 54; 76 - exit to the ele

, Q “with

20 25 lp

ment-OR 63; 77 - output element

45

0

five

And 65.

To ensure the operation of the device with an operational storage device (Fig. 3), there are two information arrays M1 and M2 in n words each, where n is the number of channels served and the output information area, which is successively filled with words containing the sign with the channel number.

The word H of the array includes the reference values of the counter of 10 pulses, the counter of 14 pulses, the discharge with the sign of the bi-polarity of the parcel in the channel.

The word array M2 comp. from chet: - rex the floor to her 5 in which I write down .-. The current state of the reversing chick is 95 counter 10 pulses, counter 14 parcels and register 16 shift.

The output information is recorded through a multi-chip data box (Fig. 3) into the operational memory of the device outputs 19 and 23.

The device works as follows.

Before starting the operation of UBM, through the trunk of the complex (Fig. 3), it zeroed operational 33 and recorded the tuning information in masses Ml. Then, the initial setup signal (CU) is sent to the input 4 of the device, which resets the 6th channel into O. figure 1), the counter 50 cycles and trigger 53 (fkg, 2) with

The operation of the device takes place according to clock cycles T1. T5, which are formed at the outputs of the decoder 51 (respectively I through V) from the input clock pulses 1 (Fig. 4) with the help of a 50 clock clock counter.

Informational inputs 5 of the device (Fig. 1) are transferred character-wisely from the remote terminals from remote terminals by a stop-by-stop method. Each character consists of a set of bits. The value of the bits is transmitted along the line of the unipolar line and the dual field by the girl.

The symbol is accompanied by starbyBY (zero polarity of the parcel) and stop (single polarity of the day) bits

In the T1 cycle (Fig. 4), a request is made to the on-line memory to read the information about the previous state.

channel from the array M2. Through the element OR 52 (FIG. 2) is set to 1 flip-flop 53, and from the output 20, the call to RAM signal Request 1 goes to the priority register of the transmissions (FIG. 3). At the same time, at the output of the PT / PF mode, paragraph 21, the Read mode is formed. The address (device outputs 22, 23) goes to the address multiplexer, which is controlled by signals, from the output of the priority register of the transmissions. The address of the first word of the M2 array is fed to the ardes bus of the operational memory. Simultaneously with the address from the outputs of the priority register of the transmissions to the control inputs of the operational memory, the Inversion signal and the Read mode follow. After on the output data bus of the on-line memory, according to the information information, the signal input 2 of the device receives a response signal from the memory, which resets the trigger 53 and the signal Request 1 at output 20 (in block 3). From this signal, through the element 55 at the output 20 of the control unit 3, a tracking signal is generated, which is fed to enable writing to the reversible counter 9, pulse counter 10, shift register 16 and to the control input of the multiplexer 15. Writing permission to counter 14 The dressing is formed through the element OR 66 at the output 41 of the control unit 3. The data from the M2 array of the operative memory is received at the information inputs 24, 25, 30 and 31 of the device, which are respectively connected with the inputs of the pulse counter 10, the reversible counter 9, the shift register 16 and the multiplexer 15. The information send counter 14 is recorded from the multiplexer 49 outputs 15.

In T2 cycle, the high-order address of the address is modified (output 22) by selecting the Ml array. The request and mode are also generated as in T1. The response signal from the memory passes through the element And 56 (the output 37 of the control unit 3) and gives permission to record information in the register 16 constants on the inputs 24 and 31 of the device.

A switch of 7 channels according to the meter readings of 6 channels connects the next channel to. the input of the decoder 8 polarity parcel.

In the TK cycle, the signal from the III output of the decoder 51 increases the pulse counter state 10 by one unit and arrives at the sync input of the decoder 8 polarity of the parcel, forming at outputs 33 and 34 a summing or subtracting pulse that arrives at the reversible counter 9.

0 If at the moment the polarity of the dressing is O, then a totaling pulse is formed at the output 33, and if the polarity of the parcel is 1, then the subtracting pulse at the output 34,

5 When the state of the pulse counter 10 is equal to N (the number of gating pulses in the parcel), the output of the high-order bit is generated at the output 47 of the comparison circuit 11

0 counter 61 pulses (figure 2). The signal 42 from the output of this bit commutes the polarity of the output signals of the decoder 8 polarity of the day, arrives at the register shift 16

5 shift and the account in the counter 14 sketches (figure 1). The coincidence of the signals 42 and 47 on the element And 62 generates a signal 73J which through the element OR 63 and the element And 64 forms in the beat T4

0 reset the reversible counter 9 and the high bit of the counter 61 pulses (signal 44 at the output of the control unit 3).

one

5 Minor bits of the pulse counter 10 are also dropped in the middle of the dressing (if it is bipolar) by signal 47 through the element OR 67 and element AND 68 (the signal 40 at the top

0 control unit).

When receiving the starting parcel, the state of the sprinkler counter 14 - O and the outputs of 28 bits of this counter, - arriving at: And 54, give

5 t at the output 75 (figure 2). If at the same time the state of the most significant bit is I of the reversible counter 1 (output 35), which corresponds to a single stop,; polarity, then, at the output 71 of the element AND 60, a reset of the counter of 10 pulses through the element OR 67 and the element And 68 and the reversible counter 9 through the element 1-ISh 63 and - is formed. element 64 (outputs 40 and 44 blocks

5), after resetting the pulse counter i and the reversing counter, the search for the starting parcel begins again. If the parcel of the starting field, then at the output 75 of the element

And 54 is O, and the pulse counter 10 counts until overflow.

The state of the counter 14 sumshook is compared with the value of N1 (the number of sums in a sign) and, if they are equal, then the output of the comparison circuit plays a signal that copies the sign from the shift register to the buffer register 17, enters output 18 of the device and follows the priority register of the transmissions as a request to write to the operational memory of the generated character (output 19) and the channel number (output 23). At the same time, the signal Sigal output 18 of the device modifies the address of the output information zone using the address modifier (fig.) Address of the output information zone from the output of the address modifier through the address multiplexer arrives at the address inputs of the operational storage device. information inputs of operational memory. At the same time, from the outputs of the priority register of the transmissions to the control inputs of the operating memory, the signal should go to the write mode.

At the output 77 of the element 65, the resolution is written to the counter 14 via the element OR 66. This opens the information inputs 48 and 43 of the multiplexer 15 where O is received respectively and the signal from the output of the element 59, which analyzes the polarity of the last sending of the 16 shift register - raj being the stop bit of a character. If the polarity of the first I, then O. O is present at the output of the 43 element 59. At the same time, the lower 14 of the counter, 14, as well as in the remaining bits, is recorded. If the polarity of the first O, which indicates unreliability of the sign, on the low-order counter of counter 14, the poppy is recorded as 1, this corresponds to the state of Start found. Thus, the starting position in place of the stop accept-. for a new start, and the device continues to dial the character, automatically synchronizing reception to the start. In order to avoid accidental failure of the counter 61 (senior pulse counter), it is reset together with the reversible counter 9 after dialing a signal from the output 18 of the device through the element OR 63 and the element 64 in O (output

44 control units).

In the step T5, the states of the reversible counter 9, the pulse counter 10, the counter 14 suction and the shift register 16 (device outputs 26-29, respectively) are recorded through the data multiplexer into the array M2 of the operative memory (FIG. 3). 20, a device request 1 is generated, and at output 21, the mode

records that go to the priority register of transmissions.

The address of the array M2 (outputs 22, 23 devices) through the address multiplexer is fed to the address inputs of the operational memory (fig.Z).

five

0

five

0

five

0

five

Appeal and Mode signals are generated at the output of the priority register of the transmissions;

The response signal from the operative memory on input 2 of the device is set in O, a trigger 53 and one unit is added to the counter of 6 channels through element 57. At this, the processing of information on the next channel ends.

In the timing diagram (FIG. 4), several states are given which are possible during channel processing.

In the i-M processing cycle, a regular analysis of the polarity of the parcel occurs, and if the state of the counter 10 pulses is less than the reference one, then one is added to it,

In the J-M cycle, the state of the pulse counter is equal to the reference one and at the output 47 of the comparator unit 11 a signal is generated to write the high-order reversing counter (output 35) to the shift register 16 and reset the pulse counter and the reverse counter (outputs 40 and 44, respectively, of the control unit),

In the kM cycle, the state of the pulse counter and the downstream counter are equal to the reference values. At the outputs 47 and 18 of the comparison circuits 11 and 13, signals are written to the shift register 16 and to the buffer register 17, as well as resetting the counter 10, reversing counter 9 and counter 14 sucks.

In the 1st cycle, the state of the counter is a bit O, i.e., the Start Search mode. In this state of exit 35

916

reversible counter 9 - 1, which corresponds to a false start. In this case, the pulse counter and reversive counter are reset from outputs 40 and 44 of control unit 3, and the search for a start is restarted. In the; t) -th cycle, the state of the pulse counter and the parcel counter is equal to the reference values, and the least significant bit of the shift register (output 36) is equal to O, i.e. in the typed mark, the starting parcel appeared at the place of the stop parcel. In this case, the low order bit of the parcel counter is recorded 1 on the output 43 of the control unit, which corresponds to the Start condition found.

Claims (1)

Invention Formula A device for interfacing the telegraph lines with a digital computer, containing a control unit, a decoder for the junction slug, the first and second outputs of which are connected respectively to the summing and subtracting inputs of a reversible counter, a shift register, the outputs of which are connected to informational inputs the buffer register, the sending counter, the counting input of which is connected to the clock input of the shift register, the pulse counter, the counting input of which is combined with the synchronous input of the parser polarity, the outputs of the buffer register The first group of outputs — devices for connecting a digital computer to the data bus — is necessary because, in order to improve the performance and utilization of equipment, a channel counter, a switch, The constants register, the two comparison units, the multiplexer, the sync input and the logic input of the control unit are respectively the device inputs for connecting to the clock outputs and the response of the digital computer, gating the input and input of the control unit are connected to the output of the first comparison unit and way out the indication of the polarity of sending the register of constants, the recording permission input of the control unit is connected to the output of the second comparison unit, with the enable input of the buffer register and is the device output for connecting to the digital input synchronous input, 2 0 5 i j 5 0 5 ten the output is connected to the output of the minor register of the shift register, the output of the higher discharge of the reversible counter is connected to the reset input of the control unit and the shift input of the shift register, the reset input of the control unit is the input of the initial installation of the device, and connected to the reset input of the channel counter, a group of inputs of the logic conditions of the control unit is connected to a group of outputs of the sending counter and is a group of outputs of numbers of the device, the first and second outputs of the control unit are connected respectively with the input of the register of constants and with the counting input of the pulse counter, the third output of the control unit is connected to the inputs of the record of the pulse counter, reversible counter, shift register and the control input of the multiplexer, the fourth and fifth outputs of the control unit are connected respectively to the reset input of the pulse counter and with the entrance records of the parcel counter, the pinned output, the control unit are connected to the counting input of the counter and allowing it.} The input of the polarity decoder the feed, the seventh and eighth outputs of the control unit are connected respectively to the low-order input of the first group of information inputs of the multiplexer and the reset input the reverse counter, the ninth output of the control unit is connected to the counting input of the channel counter — the tenth and eleventh outputs of the control unit are, respectively, the high-resolution outputs of the address and mode devices for connecting to a digital computer, the twelfth output of the control unit is a device request output for connecting to a digital computer, a group of information inputs, a switch is a group of device inputs for connecting to telegraph channels, the outputs of the channel counter are connected to the control inputs of the switch and are address outputs devices for connecting to a digital computer, the switch output is connected to the information input of the polarizer decoder, the first group of information inputs of the device for connecting to the bus is given s digital computer connected to the installation and the first input pulse counter eleven the group of information inputs of the register of constants, the group of installation inputs of the reversible counter is the second group of information inputs of the device for connection to the data bus of the digital computer, the second group of information inputs of the multiplexer is connected to the second group of information inputs of the register of constants and is the third group of information inputs of the device for connection to The DVR bus, the first and second groups of outputs of the register of constants, are connected respectively to the first groups of information inputs of the first and the second comparison blocks, the second groups of information inputs of which are connected respectively to the outputs of the pulse counter and the sprinkling counter, the outputs of the counter 0339212 Pulses are the second group of informational outputs of a device for connecting to a data bus. Digital computer, first group of information inputs  the multiplexer, besides the low-order bit, is connected to the zero potential bus of the device, and the outputs are connected to the information inputs The jj counter of the counter, the group of information inputs of the shift register is the fourth group of information inputs of the device for connection to the data bus of the digital computer, the group of outputs of the shift horn is the third group of information outputs of the device for connection to the data bus of the digital computer, the group of outputs of the reversible counter is the fourth group 20 information outputs of the device for connection to the data bus of a digital computer. Phage, t  : ncci} C Ji8o co-vzlönie gpklea adzny x jiwuii Fe fisu With USM  - / 1 /, U / l- - Stl2H  With USM - - Stl2H fg 23 1914 25 50 SI I Faye. four Compiled by A. Zasorin Editor T. Lazorenko Tehred L. Serdgakova Corrector T. Malets Order 3386 Circulation 566 All-Union Scientific Research Institute of State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 4/5, Moscow, Zh-35, Raushsk nab. 113035 Subscription