SU1522154A1 - Multicoordinate digital linear interpolator - Google Patents

Abstract

The invention relates to a technique for the automated control of production processes and can be used in numerical control systems for machine tools. The purpose of the invention is to simplify the design. The interpolator contains an interpolation control unit 1, an information exchange control unit 2, an evaluation function block 3, a two-coordinate linear interpolation block 4, two memory blocks 5, an OR 6 item, a shift register 7, a movement counter 8. The interpolation is performed at the maximum possible frequency over the cycles in the coordinates of the master-slave, with the memory of the distribution of the cycle steps in the memory block in the form of one N - output shift register. 1 hp f-ly, 3 ill.

Description

The invention relates to a technique for the automated control of production processes and can be used in numerical control systems for machine tools.

The purpose of the invention is to simplify the interpolator.

Figure 1 shows the functional diagram of the interpolator; on Aig.2 - block diagram of the evaluation function; FIG. 3 is a diagram of an interpolation control unit.

The interpolator contains an interpolation control unit 1, an information exchange control unit 2, an evaluation function unit 3, a two-coordinate interpolation unit A, two 5-unit blocks, an OR 6 item, a shift register 7 and a displacement counter 8.

Block 4 of two-coordinate interpolation consists of register 9 of the leading coordinate, register 10 of the slave coordinate, switch 11 of two inputs per output, combinational adder 12, register 13 of the dryer, and inverter 14,

Unit 3 of the evaluation function contains the inverter 15, the trigger 16 characters and the element And 17.

The interpolation control unit 1 includes a pulse generator 18, triggers 19 and 20, elements 21-24, first counter 25 cycles, counter 26 cycles, second counter 27 cycles, element 28, elements OR 29 and 30, and RS flip-flop 31.

Linear interpolation in coordinates X, X ,, ..., X is conducted on an accelerated time scale over the cycles in one block 4. In the first cycle, the leading coordinate is X4; the leading coordinate is X4; in the nth cycle, the leading is X, where each cycle consists of m interpolation cycles. For the leading coordinate, it is assumed that the increments X (, X5, ..., X "which is the largest in this frame, i.e. XX (. Physical assignment of the leading coordinate to any of the coordinates Xd, is not

is required. In the interpolation in each of the interpolated planes, an evaluation function is used.

cf,

 -LH ". Hbe (q,

Where

irvan

X,

X

the maximum value of the set LH ,, fiXj, ...,. .., L

increment by the X coordinate in this frame; the current value of the X coordinate after completing i steps along the interpolated segment from its initial point, with the beginning of the segment being

at the origin, i.e.

Y -Y ° -. l - l.1 - .., - l „-and.

X

ed is the current value of the leading coordinate after performing j interpolation steps; as for other coordinates.

The rule divides the coordinate plane in the coordinates of Hved-Hz into two parts, in one of which.; 0 to

Ok

another Ojj -iO, and if the current point of testing is on the most direct one, then 0. If (ij O, it takes a step along the leading coordinate and a new value of the evaluation function is calculated, 5 fj - & XK. If (jl h Oh, then a step is taken along the coordinate X c with the calculation

C, i and

moji

five

0

five

0

five

The sign of the evaluation function unambiguously indicates which of the coordinates should yield the next step, and the next value of the evaluation function is calculated by simple arithmetic operations using the above recurrence relations.

With the arrival of a signal Reset to the second input of block 2, the latter outputs the necessary combination of signals by recording the original information19 and for interpolation from a program block (not shown) to block 5. The address is fed to the third inputs of all blocks 5, the Sample signal to the second inputs of block 5 , Record signal - to the first inputs of block 5. At the initial address, the block LH is entered into the first block 5. In the second block, the initial value of the evaluation function (p 0 and its sign is entered. After each record, the address is incremented by one. At the last address in the first .block 5 is inserted bH, The second block 5 is an OQ O and its sign. The value is directly entered into register 9.

Before each frame begins to work, a Reset signal arrives at the circuit input, which sets the counters 25 and 27 to O, and the number (n-1) is entered into the counter 26, where n is the number of coordinates of the interpolator. The End of Information Change signal passes through the AND 28 element and the OR 29 element, sets in one state the trigger 31, which allows the interpolation clock fu to pass through the AND 21 element to the block output. At the output of the counter 25

From the second output of block 1 to the first input of block 3, pulses of frequency c are received for interpolation involving the magnitude of the increment of the first coordinate. In block 3, the sign of the current value of the evaluation function, jj, is stored. Depending on the sign, the next impulse fu must pass to the output along the leading coordinate or one of X | -Hn (in the first cycle, along the X coordinate,). The sign of: also determines which of the interpolator registers is connected to the first inputs of the combination

A signal is sent to its input of a post-adder adder, in the register which contains m interpolation pulses fu. ry is J,. The value of -j. This signal means that it is completed from the register 13 of the adder is applied for one cycle. It transfers into zero the second inputs of the combinational summation trigger 31, which is block 12. Consequently, at the outputs of the combinational adder, there is the next value of the estimator function, which by the next pulse fy will be written into the memory of the adder.

Denote with f; - S - the current value of the estimated estimated function №1I.

kaet the passage of the frequency f through the element And 21. It also arrives at the input of the counter 26, one is subtracted from the contents of KQ-th, and also passes to the output of the block as a signal Information change.

On signal The end of the change of information arriving from block 2, the operation of block 1 is resumed and proceeds as described. In the last nth cycle, the counter 26 overflows. The zero potential appearing at its output goes to the output of the block to start the speed reference block and prevents the signal from passing. End of the information change through the And 28 element.

f to ° t + M.

Its next value is (J i-nj. If (, and ((.j Sf 0. If JJ and S have the same signs, then the next two steps 30 will be on the leading coordinate, since its increment is the greatest in this frame. In this case the next impulse fu should go to the exit only by the coordinate of the coordinate. If c and 5 ,, there are different signs, but oh,

At the output of counter 27, a signal appears that determines the next step in the lead

when it receives m pulses from the speed reference block. This signal again sets the number (p-1) in the counter 26 and, through the element OR 29, sets the trigger 31 to the one state, i.e. operation of block 1 is resumed from the first cycle. From the outputs of the And 22-24 elements, the frequencies fp, f.af, E, fqsc are received continuously at the output of the block and are fed to block 2 for organizing write-read modes in block 5 of the RAM.

After recording the initial information, block 2 sets the starting address and signals from its second and fourth outputs to transfer words to block 4 from all 5 memory blocks, and also sends a signal to the end of the information change to block 1. Thereafter, block 4 is prepared to the first interpolation cycle in coordinates. On signal End of change information

Denote with f; - S is the current value of the estimated estimated function №1И.

f to ° t + M.

Its next value is (J i-nj. If (, and ((.j Sf 0. If JJ and S have the same signs, then the next two steps 0 will be on the leading coordinate, since its increment is the greatest in this frame. In this case the next impulse fu should go to the exit only by the coordinate of the coordinate. If c and 5 ,, there are different signs, but oh,

what determines the next step in

five

coordinate, it is possible to make the diagonal pin on two coordinates simultaneously — the leading and Xk. On the next interpolation cycle, the o and signs (1 will again be different (another two clock pulses cannot pass through the coordinate in a smaller increment), and the 0 sign will determine the step in the X coordinate, which was already done at the diagonal step on the previous cycle, i.e., at S o, the output is empty, without taking a step.

Each new value of the evaluation function is calculated in the adder by summing the numbers of different signs: at S 7f О (St., BI - аХк, at (Jt О L + & Xr, and if d, then the adder overflows. Consequently, the output of the adder is a signal if (D (0, and S 0, if

71522154

it can be seen, 4TO (3t +, determines the future step along the leading, coordinate.

Therefore, the shift buffer register 7 should be filled according to the following rule: the inverted signal from the output of the combinational part of the adder is fed to the information input of the register, and the step shift along the leading coordinate from the output of block 3 is fed to the shift input. a step is made only along the leading coordinate, then O is entered in register 7, if 8

ten

the code of steps for the X coordinate is calculated. This code enters the register 7 and fills its first m bits, shifting the previously entered code on the X coordinate into the second group of bits and bits.

After the second cycle of interpolation, information is exchanged between blocks 4 and 5 in the same way as the exchange described after the first cycle. The number of such cycles is n, where n is the number of coordinates for a given interpolator. After m steps out

Dits diagonal step (Jt 0, J /,: 0),; j5 leading coordinate in the nth cycle also

then in register 7 is entered 1, at 0 and 0 |., shift and change of the contents of register 7 is not made. If by some coordinate DH, .to t and Sl constantly have different signs. Then, in this interpolation cycle, register 7 is filled with units at each shift cycle.

Each interpolation cycle is determined by m steps along the leading coordinate (the number of pulses η can be from m at up to 2 m at LH, (AXmai {) In this case, the output steps code fills the next m bits of the shift register 7. The bits of the register 7 are personal The first m bits are used to write the code of steps along the Chl coordinate, the second m bits - along the X coordinate, .., etc. The last m bits serve to write the code of steps along the X coordinate,

After n steps in the leading coordinate, the first cycle ends, block 1 prohibits the arrival of clock pulses f c, and at its first output

20

25

thirty

35

information is exchanged between blocks 4 and 5 under the control of block 2, with the only difference that from block 4 two words are transmitted to block 5 at the last nth address, and block 4 enters p, va words read from block 5 at the starting address. This means that the words that were written in block 5 after the first interpolation cycle, i.e. The state of block 4 is restored to continue the interpolation in the coordinates of Xyd-X.

I

By this time, all bits of register 7 are filled with the code for the distribution of steps over coordinates in m cycles. Signal The end of the change of information after the n-th cycle from block 2 to block 1 does not arrive at the end of the exchange of information between blocks 4 and 5. Block 1 generates a signal at its output, which is fed to the start of the block, setting the speed. From the block

.. -ts, „- -, .- Q speed assignments start coming in

Signal change is generated.

signals with the programmed frequency ff through the element OR 6 on the shift roBbrii register 7 and input block 1. The last bit in each of the groups in m bits of register 7 is the output along the corresponding coordinate (i.e. bits with numbers ha, 2t, 3t, etc.). At the outputs of these bits, with the frequency specified by the program, control signals are generated by coordinates depending on the codes recorded in these areas of the register. 7. After m impulse speeds fj from the task setting block, block 1 unlocks the arrival of frequencies to block 3.

It is fed to the first input of block 2. Block 2 generates a combination of signals for recording information from block 4 to block 5 at the previously set (initial after the first cycle) address, i.e. In block 5, two words are entered: DH, and its sign. After this, block 2 increases the address by one and generates a combination of signals to match the signals from block 5 and transmit two new words to block 4: DX (and the initial value fjfo and its sign. Block 4 is prepared for the second interpolation cycle, and block 1 is fed signal End of information change, which unlocks the arrival of fts.

In the second 1 click on interpolation, there are steps along the leading coordinate

eight

the code of steps for the X coordinate is calculated. This code enters the register 7 and fills its first m bits, shifting the previously entered code on the X coordinate into the second group of bits and bits.

After the second cycle of interpolation, information is exchanged between blocks 4 and 5 in the same way as the exchange described after the first cycle. The number of such cycles is n, where n is the number of coordinates for a given interpolator. After m steps out

the leading coordinate in the nth cycle is also

0

five

0

five

information is exchanged between blocks 4 and 5 under control of block 2, with the only difference that from block 4 two words are transmitted to block 5 at the last nth address, and p, va words read from block 5 are entered into block 4 at the starting address. This means that the words that were written in block 5 after the first interpolation cycle, i.e. The state of block 4 is restored to continue the interpolation in the coordinates of Xyd-X.

I

By this time, all bits of register 7 are filled with the code for the distribution of steps over coordinates in m cycles. Signal The end of the change of information after the n-th cycle from block 2 to block 1 does not arrive at the end of the exchange of information between blocks 4 and 5. Block 1 generates a signal at its output, which is fed to the start of the block, setting the speed. From the block

0

five

signals with a programmed frequency ff through the element OR 6 on the shift Bbrii input register 7 and to the input block 1. The last bit in each of the groups in the m bits of register 7 is the output along the corresponding coordinate (i.e. with numbers ha, 2t, 3t, etc.). At the outputs of these bits, with the frequency specified by the program, control signals are generated by coordinates depending on the codes recorded in these areas of the register. 7. After m impulse speeds fj from the task setting block, block 1 unlocks the arrival of frequencies to block 3.

In the future, the operation of the device is carried out in cycles from the first to the n-th in accordance with the

91

description. But all n interpolation cycles must be performed in a time shorter than the f-signal period from the speed reference block. In the counter 8, which works on subtracting the pepper, the beginning of the development of the plot, the value is entered. Each pulse ff is fed to the input of the counter 8. The overflow signal of the counter 8 indicates the end of interpolation.

The maximum feed the device can provide is proportional to the frequency at the output of the speed reference block :,

,, 60 f yay ta h y

where is the maximum frequency at the output of the speed reference block;

h is the value of a single interpolation step, mm, corresponding to a single pulse from the output of the speed reference block. In the proposed device should

condition T is met. I®

tu, is the time of one interpolation cycle

If (O, then the trigger 16 is in the zero state, if with C: O in one. At 0, the interpolation pulse passes through the element 17 to the output along the leading coordinate. At the entrance With the falling front of this pulse, the sign 16 is written to the trigger 16 function S, whose value is fed to the input D of the trigger 16 in the form of an inverse signal overflow of the combinational adder 12.

The output of the trigger 16 controls the switch 11 of the two inputs to one output, which thus, depending on the sign c, connects to the combination adder 12 either the register of the leading coordinate 9 or the register of the coordinate XK, and the number from the register 9 is transferred to the forward code, from register 10 - in addition. The second input of the adder 12 is supplied with the current value of the evaluation function c (both in the forward code and in the supplementary mode at (0. Thus, at the inputs of the mater 12, one term is always represented in the forward code, the other is in the extra one. If the result of the sum is positive, then

ten

five

Q

0

0

50

5 0 e

replenishment of the adder, i.e. if, then S 1, and vice versa, if (Si (0, then S 0. Thus, the inverse value of the overflow signal of the combinational adder 12 S will represent the sign с, 4. Simultaneously with writing the sign di "f to the trigger 16 with the same the pulse fc value (Jt-K is written to the register 13 of the adder.

Blocks 1 and 2 are similar to those presented in the prototype, except that the number (p-1) -1, entered in block 1 to change the number of interpolation cycles, is constant in this scheme and input of this value is not required.

Claims (2)

1. A multi-axis digital linear interpolator containing, when interpolating along n coordinates, a two-coordinate interpolation block, whose information input is connected to the first output of the evaluation function block, the input input of the two-coordinate interpolation block, is connected to the first output of the information exchange control block, outputs address - - tions, samples and records of which are connected to the corresponding control inputs of the first and second memory blocks, the information output - to the information input of the interpolation control block, whose clock frequency is connected to the first information input of a multi-coordinate digital linear interpolator, the Start output of which is connected to the first output of the interpolation control unit, the second output of which is connected to the second input of the two-coordinate interpolation unit and the first input of the evaluation function block, the second input of which is connected to the first output of the two-coordinate interpolation block, the input of the input of which is connected to the second information input of the multi-coordinate digital linear interpo torus, third information input of which is connected to the input of input displacement counter, and output - with output displacement counter, a third control unit out interpolation is connected to the first input of the control unit of information exchange, the second whose input is connected to the Reset input of a multi-coordinate digital linear interpolator, the second output of the linear interpolation block with the information input of the second memory block, and the OR element, characterized in that, in order to simplify the design of the interpolator, an n-output the shift register, the information outputs of which are connected to the information outputs of the multi-coordinate digital linear interpolator,. information input - with the first output of the two-coordinate interpo-block, and the shift input - with the output of the OR element, the first input of which is connected to the second output of the evaluation function block, and the second input - with the first information input of the multi-coordinate digital linear interpolator with clock input counter FIG. g Fig.E displacements, the third input of the evaluation function block is connected to the output of the second memory block and to the third information input of the two-coordinate interpolation block. I: 2. Interpolator according to claim 1, characterized in that the block is estimated. the night function contains a trigger of the sign, the element NOT and the element AND, the output of which is connected to the second output of the evaluation function block, the first input with the inverse output of the trigger of the sign, The R-input of which is connected to the input Reset of the evaluation function block, the D-input to the second input of the evaluation function block, the C input of the element is NOT connected to the first input of the block the evaluation function, the third input of which is connected to the S-input of the sign trigger, the second input of the element AND is connected to the input of the element NOT. Watoftk ffjy ffc ffvtc iaic