SU1095189A1 - Digital adaptive linear interpolator - Google Patents

Abstract

1. A DIGITAL ADAPTIVE LINEAR INTERPOLATOR containing a clock generator and a sequentially-connected storage register and accumulating adder that has four real-time shift registers, to ensure linear interpolation of processes in the presence of noise in real time. , multi-adder, interpolation interval calculating unit, increment calculating unit, term array formation unit, key and switch, with the outputs of multi-digit cells of the first and second regis The shift level is connected to the inputs of the adder, the output of the first shift register is connected to the information inputs of the second and third shift registers, the output of the multi-input adder is connected to the first information input of the increment calculator, the output of the sync pulse rekerator is connected to the sync inputs of the first, second, third interpolation interval calculator and fourth shift registers, KEY0, VGRO accumulator | Shd:: - ft. and the third synchronized input of the array of the components of the addends, the control input of the interpolation interval computation block is the second interpolator input, the information, the first and the second sync outputs of the interpolation interval calculating block are output respectively to the second information, the first and the second sync inputs of the increment calculator,. interpolation block interpolation block interpolation is connected to the information input of the fourth shift register; information input of the array formation block are connected to the output of the increment calculator, the first and second (L sync inputs of the ad unit array formation are connected to the first and second sync outputs of the interpolation interval calculator, respectively, the output of the third shift register is connected to the input of the storage register, the output of which is connected to the first the information from the inputs of the accumulating adder and the switch, the output of the fourth register SP shift is connected to the control inputs of the key that accumulates the accumulator and the switch, the output of the photomultiplier The addendum array is connected to the second information input of the accumulating adder, the key output is connected to the storage register entry, the accumulator accumulator output is connected to the second information input of the switch, the switch output is the linear interpol.ch output, and the first shift register information input is first interpolator input.

Description

2. A linear interpolator according to claim 1, characterized in that the interpolation interval calculating unit comprises the first element AND, the fifth and sixth shift registers in series, the pulse leading edge selection unit, the output of which is connected to the R input of the R5 trigger, and also is the sync output of the interpolation interval calculation block, 5 INPUT R5-TRIGGER is connected to the output of the first AND element, the output of R5-TRIGGER is connected

with the input of the front-edge selection node and the second input of the second element AND, as well as the output of the interpolation feature of the interpolation interval calculating unit, the output of the second element AND is connected to the counting input of the binary counter, and the output of the front-edge impulse node is connected to the installation input the zero of the binary counter is the first synchronized output of the interpolation interval calculation block whose information output is the output of the binary counter, the first inputs of the first and second elements, AND, and the clock terminal of the fifth and sixth shift registers are combined and the clock unit interval calculating interpolation control CIM to which input is the second input of the first element I.

3. Linear interpolator according to claim 1, characterized in that the increment calculating unit contains the second and third storage registers, the subtractor and the divider, the information inputs of the registers are combined and are the first information input of the increment calculating unit, the outputs of the second and third registers are connected respectively to the inputs subtraction and layer

A subtractor whose output is connected to the information input of the divider, the first information input and the output of the divider are respectively the second information input and output of the increment calculator, the first and second sync inputs of the increment calculator are respectively connected to the second storage register and the third storage register and the divider .

4. Linear interpolator according to claim 1, characterized in that the block of forming the array of components contains a register of private and delay elements, the installation inputs of all cells of the register of private shift are combined and are an information input of the block of formation of the array of components, the output of which is The output of the private shift register, the control inputs of the keys are combined and are the second synchronizing input of the array of the components of the addendum, the first synchronizing input of which is the input of the delay element, bus shift shift register the shift characteristics of the record and the shift register of the quotient are combined and are the third synchronous input of the array formation unit, the output of the delay element is connected to another record shift register entry, the serial input of which is connected to the optical zero bus, the setup inputs of the recording attribute shift register are connected to the logical bus units, the output of the cells of the register of shift of the attributes of the record is connected to the information inputs of the keys, the outputs of which are connected to the recording inputs of the corresponding cells of the gistra shift private.

The invention relates to the processing of experimental information and can be used in real-time operation for linear interpolation of the

battered processes in the presence of additive yums and impulse noise. In the practice of processing experimental information presented in the form of random processes, often

a situation arises when the processing process y (t) contains, along with the useful signal (process) 5 (t), the component of the additive noise Pn (t) and the component of impulse noise n (-t)

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t p

1) a) 5a) + pc, (h) -p1, “pa). (about

Such conditions are typical when transmitting information via channels with noise and impulse noise, in particular, in radiolocation, radio communication, telemetry, as well as for digital information processing in the presence of equipment failures, during phonogram recovery

The elimination of the influence of impulse noise in the processing of the original process is achieved by interpolating the process in the intervals of the existence of impulse noise.

Interpolators that produce linear, linear-circular and non-linear interpolation of deterministic processes are known.

However, nonlinear interpolators are difficult to implement and do not allow real-time processing of random processes.

The linear interpolator 2J, taken as a prototype, contains a pulse generator, a reversible counter, a storage register, the output of which through a set of matching circuits is connected to the input of the accumulating adder. The meter subtraction input is connected to the output of the pulse generator. The input of the initial installation of the counter is the first input of the interpolator — a binary code corresponding to the length of the interpolation interval is fed to this input. The second input of the interpolator is the setup inputs of the storage register, to which the number corresponding to the tangent of the angle of inclination (to the time axis) of the interpolated straight line is applied. The source data is entered into the reversible counter and the storage register before the pulse generator is turned on. When the pulse generator is turned on, a sequence of pulses is fed to the input of the subtraction of the reversible counter, as well as to the second input of a set of coincidence circuits. When the counter is zeroed, the output of the count appears at its output. By the appearance of this pulse, the interpolation process ends. During the counting process, the sum at the output of the accumulating adder on receipt of the next countable

the pulse is increased by the value entered in the storage register.

A disadvantage of the known linear interpolator is that when interpolating it is necessary to know in advance the slope of the direct (to the time axis and the duration of the interpolation interval (D)). When processing real-time experimental information specified in the form of processes, there is no such data - the slope of the direct and the duration of the interpolation interval (i.e. the duration of the impulse noise) can be arbitrary. In addition, in the presence of the processed component lj (t) of the noise component hjj, (t) the direct determination of the slope of the inte polishing straight on interpolation interval (i.e., the derivative of the process 5 (i) difficult.

The purpose of the invention is to provide linear interpolation of processes in the presence of real-time noise.

The goal is achieved by the fact that a digital adaptive linear interpolator containing a clock generator and a sequentially included storage register and accumulating adder also contains an additional four shift registers, a multiple input adder, an interpolation interval calculator, an addendum calculator, an array of addendum, key and a switch, with the outputs of the multi-bit cells of the first and second shift registers connected to the inputs of the adder j output of the first shift register n with information inputs of the second and third shift registers, the output of the multi-input adder is connected to the first information input of the increment calculator, the output of the sync pulse generator is connected to the sync inputs of the interpolation interval calculation block of the first, second, third, and fourth shift registers, key accumulating adder and third the sync input block of the array of components of the addends., the control input of the interpolation interval calculation block is the second interpolator input, the information input, he first and second clock terminal interpolation interval calculating unit tion are connected respectively to the second informational

the first and second sync inputs of the increment calculator, the x-y code of interpolation of the interpolation interval calculator of the interpolation interval are connected to the information input of the fourth shift register; with the first and second sync outputs of the interpolation interval calculation block, the output of the third shift register is connected to the input of the record of the storage register the output of which is connected to the first information inputs of the accumulator of the adder and switch, the output of the fourth shift register is connected to the control inputs of the key accumulating the adder and switch, the output of the array array generation unit is connected to the second information input of the accumulating adder key output is connected to the input of the storage register , the accumulator accumulator input is connected to the second information input of the switch, the switch output is the output of the linear interpolator, and info The input entry of the first shift register is the first input of the interpolator.

The interpolation interval calculation block contains the first AND, the fifth and sixth shift registers in series, the pulse trailing edge node, the output of which is connected to the R input of the R5 trigger, and is also the second synchronous path of the interpolation interval calculation block, A 5-input of the R5 trigger is connected to the output of the first And element, the output of the R5 Trigger is connected to the input of the pulse front edge unit and the BTOpfiiM input of the second And element, and is also a trigger for the interpolation indication of the interval interval block interpolation, the input of the second element I is connected to the counting input of the binary counter, and the output of the front-edge selection node is connected to the input of the binary counter zero input and is the first sync output of the interpolation interval calculator whose information output is the output of the binary counter the first inputs of the first and second elements And, as well as the sync inputs of the fifth and sixth

the shift registers are combined and are the synchronous input of the block. the calculation of the interpolation interval, the control input of which is the input of the first element I.

The increment calculator contains the second and third storage registers, the subtractor and the divider, the information inputs of the registers are combined and are the first information inputs of the increment calculator, the outputs of the second and third registers are connected respectively to the subtractor and addition inputs of the subtractor, the output of which is connected to the information input of the divider The first information input and the output of the divider are respectively the second information input and the output of the increment calculator, the first and second synchronization inputs the increment calculating unit is connected respectively to the synchronous input of the second storage register, the synchronous inputs of the third storage register and the divider.

The addend array array generation block contains the private shift register and the delay element, the installation inputs of all the subchanges of the private shift register are combined and are the information input of the array array construction, the output of which is the output of the private shift register, the control inputs of the keys are combined and are the second synchronous block forming an array of items, the first synchronized input of which is the input of the delay element, the bus pulses of the shift register of the recording characteristics and the shift register privately O are combined and are the third synchronized input of the array of the addendum, the output of the delay element is connected to the write write register write bus, the serial input of which is connected to the logic bus, the write sign shift register's inputs are connected to the logical one bus, the shift register outputs records are connected to the information inputs of a set of keys, the outputs of the keys are connected to the recording inputs of the corresponding cells of the private shift register. FIG. 1 shows a diagram of the device; in fig. 2 is a block diagram of the calculation of the interpolation interval; in fig. 3 is a block diagram for calculating an increment; in fig. 4 is a block diagram of the formation of an array of items; Fig. 5 shows the schemes for accumulating the sum of a torus; Fig. 6 shows diagrams explaining the work of the interpolator; in fig. 7 and 8 plots of signals of the main blocks of the integrator. The device (Fig. 1) contains the first 1 and second 2 (multi-bit) shift rods with taps of cell length and the register size corresponds to the bit of the operands being processed, a multi-input adder 3 dividing the summation result by 2L, the third (multi-bit) re shift 4, length Lj, cells, storage register 5, accumulations summator 6, switch 7, interpolation interval calculation block 8, increment calculator, fourth (single-bit) shift register 10 LJ, cells, array formation block 11 terms, key 12, generator torus 13 clock. Block 8 (FIG. 2) contains the first element AND 14, the R5 trigger 15, the fifth 16 and the sixth 17 one-charge shift registers of length L cells each, the pulse edge front end unit 18, the second pulse element 19, the front end unit 20 pulse front and binary counter 21. Block 9 (Fig. 3) contains the second and third 23 storage registers, a calculator 24 and a divider 25. Block 11 contains (Fig. 4) a one-bit write character shift register 26 with a length Lj, cells, keys 27, the multi-bit register 28 is the offset of the quotient of the length Lf of the cells, delay element 29. Accumulating adder 6 (Fig. 5 contains the first 30 and second 3t Combination adders, storage register 32 and inputs 33.1, 33.2 and 34.1, 34.2. Fig. 6 shows the diagrams explaining the conditions of the interpolator, Fig. 6a is shown The process y (t) at the input of the interpolator, where 5 (t) is the useful signal (dashed lines), rqe, is indicated by the time intervals of 35 36, 37, where there is no noise interference, i.e., the process and (t) represents they are a mixture of the useful signal 5 (t) and hb, (t), impulse noise 38, 39, bi,. 2 the duration of interfering pulses, i c tm - the beginning and end of the intervals of inter Fig. 6b shows the CI pulses (interpolation command) applied to the interpolator's input from external devices at time intervals at which process i (i) should be interpolated. Fig. 7 and Fig. 8 The signal plots of the main blocks of the interpolator are shown in. Fig. 7a shows the process C (i) at the output of register 1, where 5 (ti) is the useful signal (dashed line); tiwMn (ii) impulse noise; Пщ (t;) additive noise; inQ, i 1 (4 points in time, corresponding to the beginning and end of the interpolation interval; 40, 41 - position of the memory interval of the smoothing filter at times i i and, respectively; 2 the length of the memory interval of the smoothing filter. In Fig. 7 b shows the estimated average Gotz (ti) at the output of the adder 3 (at the output of the smoothing filter), and Fig. 7c shows the interpolation command applied to the second interpolator input (Fig. 1), 2 "h the duration of the interpolation command (corresponding to the duration pulse interference); in Fig. 7 g - pulses at the output of the element And 14; in Fig. 7d, the interpolation pulses) fj, .j (i) at the output of AND 19; in fig. 7th pulse at the output of the R5 trigger 15; in fig. 7g - the pulse at the output of the node 20; in fig. 7h - the pulse at the output of the node 18; in fig. 8a shows the change in the state of the counter 21 over time, (is the number at the output of the counter 21 after the moment of time, iviq is the moment of zeroing of the counter 21; in Fig. 86 the change of the state of the register 22 over time (writing to the register is made at Fig. 8c shows a change in the state of the register 23 over time, writing to the register is made at the moment of time; Fig. 8g shows the plot at the output of the subtractor 24, and Fig. 8e shows the plot at the exit of the divider 25 (output 9). 8e and 8k show the states of the register cells 10, 26, 28 at different times. The numbering of the register cells by this their diagrams are produced from right to left.The length of diagrams corresponds to the number of cells (length Uc) of the shift registers.Fig 8e shows the state of the cells of register 26 at a time (after writing a logical unit to all register cells with a pulse from the output of element 29 (Fig. A) ; for FIG, 8g — the state of the cells of register 26 at the time; in Fig. 8h, the recording interval at time ixu of the private a into register 28; in Fig. 8i — the state of the cells of register 10 at the time of Ip (denoted by epures 7a, Over - 8d); in fig. 8g is the state of the register 28 cells at the moment of time p. The principle of operation of the device is as follows. The process to be processed 1 ((i) in a parallel binary code is fed to the first interpolator input. The plot of the process at the output of register 1 is shown in Fig. 7a (the time sampling step in Fig. 7 and 8 is shown by dividing the time axis). Register 1 and 2 and adder 3 form a smoothing filter. The number of inputs of the adder is equal to the total number of memory cells of both shift registers, i.e. equal to 2Lf. Process P1y (1;) at the output of adder 3 is shown in Fig. 76: d). (t;) - assessment of the current average process and (t). The operation of dividing (rounding) by 2L is implemented in the adder 3 blars rational choice of the lengths of registers 1 and 2. When (where K is integer), the division operation is implemented by shifting the sum result to the right by (K + 1) binary bits. In practice, L is 2–4. In the absence of noise, the adaptive linear interpolation of the process being processed is performed using Vj (ii) samples taken at the ends of the interpolation interval equal to the length of the it.-interpolation command (FIG. interpolation commands are formed by the first-order polynomial; Cha..y1 ,,, where t., 1cc, 1cz is the time moment corresponding to the beginning of the interpolation interval; i ((u is the time point corresponding to the end of the integration interval; O, - the coefficient of the polynomial, determined by the readings of process 1 (1 qi), v) (qc) .ji. (tHu) .i - bich (o where the times t, q, i correspond to the leading and trailing edges of the pulse-fiOMexH (Fig. 6a). The presence of the noise component and (-t ;) in the process ij (i) with such an interpolation procedure leads to large fluctuations of the slope of the interpolating direct, which is unacceptable with further extraction of useful information from the process being processed. The introduction of preliminary smoothing ensures a reduction in the dispersion (by a factor of 2 1) of the current average WM (1) compared to the variance of the original process U (i; j), since 1 UO. The dispersion of the slope of the interpolating straight line is reduced by the same number of times. The use of a finite-memory pre-smoothing filter having a memory in 2 L time-sampling intervals leads to features in the formation (determination) of the interpolation interval. These features consist in the fact that the duration of impulse noise n JIMP (i) passed through a smoothing filter J is increased by the value of the memory interval of the smoothing filter, i.e. 2 L sampling intervals. Therefore, in block 8 for calculating the interpolation interval (Figs. 1 and 2), the determination of the interpolation interval is made taking into account the effect of lengthening the duration of a pulse interference. Block 8 works as follows. Sync pulses from the output of the generator 13 are given to the sync input of the block. An interpolation command is sent to the control input of block 8 (Fig. 7c), the duration of which corresponds to the initial duration of the impulse noise (Fig. 7a). The first element And 14 gates a sequence of clock pulses with an interpolation command. 11 A comb of clock pulses at the output of the elements And 14 is shown in FIG. 7g. The first pulse of the comb from the output of the first element And 14, the R5-trigger 15 is set to one. The video impulse formed at the output of the trigger 15 is fed to the input of the element AND 19, to the other input of which pulses are output from the output of the generator 13. In addition, a comb of video pulses from the output of the element 14 is fed to the fifth and sixth registers 16 and 17 connected in series , each of which provides for the delay of information on the bus, time-sampling intervals. Thus, at the output of the register, 17 forms a video pulse, the shape of which repeats the shape of the interpolation command (Fig. 7c, d), and the falling edge of the video pulse is delayed relative to the original interpolation command by 21, the sampling intervals (Fig. 8e, e). The node 18 generates a ss6 MeHTijcq pulse for the end of the interpolation interval (Fig. 7h). This pulse is applied to the R-input of the RS flip-flop, setting it to the zero state. Thus, the duration of the video pulse generated at the output (5-flip-flop 15 (Fig. 7e)) is equal to b (41 + 2C, where S y, is the duration of the interpolation command applied to the input of the interpolator (Fig. 1), 2o ( interval of the smoothing filter. From the leading edge of the video pulse generated at the output of the trigger 15 (Fig. 7e) by the node 20, at the time corresponding to the beginning of the interpolation interval, a pulse is formed (Fig. 7g) supplied to the input of the zero setting of the counter 21, and also to the synchronizing output of the block. 8. At the output of the element, And 19 forms with a comb pulses j (i) (Fig. 7d), the number of which is determined by the duration of the strobe at the output of the trigger 15 (Fig. 7e). The duration of the interpolation interval is defined as the number of time-sampling pulses (Fig. 7e) from time4 to tc by counting pulses of a comb by a counter-21 (Fig. 8a). Thus, the following signals (pulses) are sent to the outputs of block 8: the information output is a number in binary code, corresponding to the length of the interpolation interval; 8912 at the output of the interpolation feature video pulse corresponding to the interpolation interval (Fig. 7e); at the first synchronizing output, the pulse corresponding to the beginning of the interpolation interval (Fig. 7g); on the second synchronizing output, the pulse corresponding to the end of the interpolation interval (Fig. 7h). Block 9 (Fig. 3) works as follows. The information inputs of registers 22 and 23 are combined and are the first information input of block 9. The first information input of block 9 is fed to the ghp process (t) from the output of adder 3 (Fig. 7b). The pulse generated at the output of node 20 and supplied to the synchronous input of the register 22 is at time t (c from the first synchronized input of block 9 to the register 22, the countdown of the process hHP () is recorded (fig. 8b). By the pulse generated at the output of the node 18 and supplied to the synchronous input of register 23 from the second syncroBlode of block 9, at time ivi, register 23 records -KCH process count (kc (Fig. 8c)) CC At time t, a difference My (t (., q) -P1ts (1nch) which goes to the second information input of the divider 25 (Fig. 8d). The divider input at the same time point is the difference (ij-vj-tHn) from the output of counter 21 (Fig. 2 and 8a), equal to the number of pulses B yH (t) in the interpolation interval (fi. 7e). on the synchronous input of the divider 25, the quotient (increment) is formed at the output of the divider (Fig. 8e) Alty; i,) - A (tH4 t h (6) which is fed to the information input of the block 11 (Fig. 4). On the first and second synchronous inputs block 11, start pulses are applied (FIG. 7g) and the end (Fig. 7h) of the interpolation interval, and the third synchronous input of the block 11 is pulsed from the output of the generator 13. The block 11 operates as follows. The quotient is applied to the installation inputs of all the cells of register 28. The number of cells (delay elements) and registers 4, 10 ,, 26 is the same and equals to c of them k D cimagg

13

the maximum duration of the interpolation command (it is determined by the working conditions of the interpolator and its specific application). Promotion of information on registers 4, 10, 26, and 28 is effected by shift pulses from generator 13. In register 1, pulses are sequentially recorded (on the information input of the register); /; ).

FIG. 8, and the information (state of the register cells) is shown in the register 10 at the moment of time to (the position of the moment of time is shown in FIG. 8 a-e).

In register 26, information is recorded from the installation inputs of the register cells by a command from the first synchronization input of block 11; from element 29, the logical unit is written to all cells of register 26. The introduction of the element 29 is necessary for spacing in time the operation of shifting information in the register 26 and the operation of recording information from the setting inputs of the register. The state of the cells of register 26 at the moment of time, q (after the arrival of a pulse Record) is shown in FIG. 8e. The input of the sequential reception of the register 26 is connected to the logical zero bus, therefore at the time of recording into the register 10 of the whole group of pulses Y (t; j) corresponding to the interpolation interval (for example, moment 1 (c in Figs. 7a and 8a) in the first cc The zero cells of the register 26 will be written to zero (fig. Vzh). The pulse from node 18 of block 8, fed to the second checkout of block 11, passes only through those keys 27, to the inputs of which prohibition logic zeros are applied (fig. 8g). the keys 27 are sent to the write cell buses of the register 28, while only these cells and the The quotient a (6) corresponding to the given interpolation interval (Fig. 8h). Thus, in each cycle of writing information to the register 28, the recording is made only in those cells that correspond to the current interpolation interval. Other cells of the register 28 are at This is in the storage mode. The state (recorded information) of register 28 at time tp is shown in Fig. 8k.

At the output of the key 12 are formed imggulsy inverse after the fact on v9518914

Lenin to impulses, (ti), i.e. when register 10 of the first pulse arrives, (ij) register 5 is transferred to the storage mode (there are no recording pulses on it 5), with

this is recorded in the countdown (). To the second information input of the adder 6 in each sampling interval of the given interpolation interval

A partial quotient is received and for each pulse of time discretization on the interpolation interval, the intermediate sum is computed with the quotient and with preservation of the new

5 results to the next. Summation cycle. Thus, the algorithm for generating 1 gi (1,) described by formula (3) is implemented. In this case, the switch 7 is transferred to the manager

0 a signal from the output of register 10 to the lower position and to the output of the interpolator are counted as Q ds (ii) outside the interpolation interval j, (tj) 0 moving contacts of switch 7

5 is transferred to the upper position and the outputs of the interpolator are readings C (i) from the output of the register 5. Reg.: Trails 4 and 10 are used to compensate for the delay of the initial process and

- interpolation decisions jj, (i), which appear when measuring the duration of an interpolation command in block 8.

The circuit of the adder 6 is shown in FIG. 5. Adder 6 consists of combinational adders 30 and 31 and storage register 32. Operands from the output of register 5 are fed to input 33.1 of adder 6. Private input is fed to input 33.2 of adder 6 and input 11.1 to input 33.2 (transfer to write mode ) Adder 6 (i.e., the input of the zero-register setting 32) signals jj Ci) are output from the register 10, while the register 32 is transferred from zeroing mode to recording mode. To the input 34.2 of the synchronizing adder 6, pulses are output from the output of the generator 13; these pulses are used to record the result of the addition from the output of the adder 31 to the register 32. In the t -th sampling interval at the output of the total 1-1

Pa 31 forms the sum (21 O + a),

5 at the same time at the output of the adder 30

(i.e., the output of the adder 6) produces the current interpolation result (trtHO. Outside the interpolation interval, the signal from the output of register 10 is zero, the register 32 is zero and the summation in the accumulating adder does not occur when the clock pulses are inserted) of the front 20 fronts are implemented as patterns of formation of short pulses from the drops. Thus, the introduction of new blocks and links between them, along with the blocks and links in the prototype, allows the following operations: with help An active filter formed by the first and second shift registers and the multi-input adder will smooth out the fluctuations due to the presence in the input process 4 (Lp noise components, (i); calculate, based on the duration of the interpolation command and the memory interval of the smoothing filter, the length of the interpol from the output of the smoothing filter, taken at the ends of the interpolation interval, and the duration of the interpolation interval, calculate the increment of the interpolated process related to one inter shaft temporary -J .. -. f -. sampling of the input pro, process (pa

the repetition period of sync sync from the generator output); to form an array of terms advancing in shift registers synchronously with the advancement of the input process, each member of which is equal to the increment of the interpolated process in the time interval;

polished direct and interpolation interval durations and. can be used in processing information transmitted over channels with noise and impulse noise (or equipment malfunction), in processing phonograms, as well as in radiolocation and radio communications. 8916 according to the signals from the fourth shift register in the accumulating adder on the interpolation intervals from the initial count of the input process (for each array) and the arrays of the addends (from the output of the ad unit of the array of addends) to form an interpolated process. The implementation of the proposed operations proposed by the interpolator ensures the interpolation of the input process by real-time interpolation commands. To interpolate with known devices, it is necessary to know in advance the slope of the interpolated straight line and the length of the interpolation interval. Such conditions of work of interpolators are characteristic and permissible1 in case of programmed control of machine tools. When processing real-time experimental information specified in the form of processes (digital sequences), such data a priori does not exist. In addition, in the presence of noise, interpolation of processes according to algorithms implemented by known devices is performed with significant fluctuations of errors. The proposed digital linear adaptive interpolator allows real-time interpolation of processes with - - C ----- -l -w a priori unknowns to the slope of the interphi. G

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Claims (4)

1. DIGITAL ADAPTIVE LINEAR INTERPOLATOR containing a clock generator and sequentially connected storage register and accumulating adder, characterized in that, in order to ensure linear interpolation of processes in the presence of noise in real time, four shift registers, a multi-input adder, a calculation unit are introduced into it the interpolation interval, the increment calculation unit, the array of terms, the switch keys, and the outputs of the multi-bit cells of the first and second shift registers connected to the inputs of the adder, the output of the first shift register is connected to the information inputs of the second and third shift registers, output ^! the multi-input adder is connected to the first information input of the increment calculation unit, the output of the clock generator is connected to the sync inputs of the interpolation interval calculation unit, the first, second, third and fourth shift registers, the key, the accumulating adder and the third clock input of the array of terms, the control input of the interpolation interval calculation unit is the second input of the interpolator, information, the first and second clock outputs of the unit for calculating the interpolation interval of the connection respectively, with the second information, first and second clock inputs of the increment calculation unit, the output of the interpolation sign of the interpolation interval calculation unit is connected to the information input of the fourth shift register, the information input of the addendum generation unit is connected to the output of the increment calculation unit, the first and second clock inputs of the addendum formation unit connected respectively to the first and second clock outputs of the interpolation interval calculation unit, the output of the third shift register with it is single with the input of the storage register record, the output of which is connected to the first information inputs of the accumulating adder and switch, the output of the fourth shift register * · is connected to the control inputs of the key accumulating the adder and switch, the output of the array of terms is connected to the second information input of the accumulating the adder, the key output is connected to the input of the storage register record, the output of the accumulating adder is connected to the second information input of the switch, the output of the switch is output of a linear interpolator, and the information input of the first shift register is the first input of the interpolator. 2. The linear interpolator according to claim 1, characterized in that ’the interpolation interval calculation unit comprises; serially connected the first element And, the fifth and sixth shift registers, the node for selecting the trailing edge of the pulse, the output of which is connected to the R-input of the R5-trigger, and is also the second clock output of the interpolation interval calculation unit, the S-input of the RS-trigger is connected to the output of the first of the element And, the output of the R5-trigger is connected to the input of the node for selecting the leading edge of the pulse and the second input of the second element And, and also is the output of the sign of interpolation of the block for calculating the interpolation interval, the output of the second element And is connected to the count to the binary counter input, and the output of the leading edge of the pulse allocation node is connected to the binary counter zero input and is the first clock output of the interpolation interval calculation unit, the information output of which is the binary counter output, the first inputs of the first and second elements, And, as well as the sync inputs the fifth and sixth shift registers are combined and are the clock input of the interpolation interval calculation unit, the control input of which is the second input of the first element I. 3. The linear interpolator according to claim 1, characterized in that the increment calculation unit comprises a second and third storage registers, a subtractor and a divider, the information inputs of the registers are combined and are the first information input of the increment calculation unit, the outputs of the second and third registers are connected respectively to the inputs subtracting and adding the subtractor, the output of which is connected to the information input of the divider, the first information input and the output of the divider are the second information input and the output of the block in computing the increments, the first and second clock terminal of the increment calculation unit connected respectively to the clock terminal of the second storage register, the clock divider and the third storage register. 4. The linear interpolator according to claim 1, characterized in that the block for generating an array of terms contains a shift register of the quotient and a delay element, the installation inputs of all cells of the register of shift of the quotients are combined and are the information input of the block for forming the array of terms, the output of which is the output of the register of shift of quotients, the control inputs of the keys are combined and are the second synchro input of the block of formation of ¹ array of terms, the first synchro input of which is the input of the delay element, bus pulses of the shift register the recording attribute shift and the private shift register are combined and are the third clock input of the array of terms, the output of the delay element is connected to the write bus of the recording attribute shift register, the sequential reception input of which is connected to the logical zero bus, the setting inputs of the recording attribute shift register are connected to the logical unit bus , the output of the cells of the register of the shift of the signs of the record are connected to the information inputs of the keys, the outputs of which are connected to the recording inputs of the corresponding cells of the reg tra Private shift.