RU2470357C2 - Location lower-bound estimate search device in fully connected matrix systems during one-way data transfer - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to digital computer engineering and is meant for simulating combinatorial problems when designing computer systems, e.g., for deploying processes (tasks, files, data, control processes etc.). The device has shift registers, a shift generating unit, a read-only memory unit, a best version storage unit, a switch, an arithmetic logic unit (ALU), decoders, a bidirectional cell counter, a random-access memory unit, counters, a multiplier, an adder, registers, comparing elements, a subtractor, flip-flops, an electronic graph model, a group of OR elements, a group of AND elements, AND elements, OR element units, univibrators, delay elements, a lower bound generating unit, having an array of adders, row counters, column counters, an array of registers, decoders of horizontally fixed arcs, decoders of vertically fixed arcs, an array of OR elements, arrays of AND elements, OR elements, an RS flip-flop and an incident vertex counter.

EFFECT: wider field of using the device owing to inclusion of location lower-bound estimate search devices in fully connected matrix systems during one-way data transfer based on the criterion for minimising intensity of interaction of processes and data.

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Description

The invention relates to the field of digital computing and is intended for modeling combinatorial problems in the design of computing systems (AC), for example, for hosting processes (tasks, files, data, control processes, etc.).

A well-known element of a homogeneous environment, including an input signal processing unit, an endpoint attribute storage unit, an output logic unit, a trace recording trigger, a current location estimation unit, an information transmission unit, inputs, outputs, a control input, information inputs, information outputs, an indicator output ( AS 1291957 USSR, class G06F 7/00, publ. 02.23.87, BI No. 7).

The disadvantage of this element is a narrow scope, due to a limited number of criteria for assessing the degree of optimal placement.

Closest to the proposed device in technical essence is a device for generating suboptimal placement and its estimation, containing a permutation generation unit, a permanent memory unit, a switch, an arithmetic logic unit (ALU), a memory unit of the best option, an arc selection decoder, a reversible cell counter are introduced , RAM block, topology counter, first and second distance counters, multiplier, adder, register of minimum connection lengths, first comparison element, subtracter, trigger Start of account, mode trigger, topology job trigger, link length register, second comparison element, arc counter, arc lock decoder, arc number register, minimum weight register, AND element group, first and second AND elements, second OR element block, third AND element, first and second one-shots, first, second, and third delay elements, two shift registers, OR element, and a group of OR elements, an electronic graph model (EMG) containing m electronic arc models, the l-th electronic arc model (l = 1, 2, ..., m) contains a trigger блокировки блокировки блокировки веса блокировки блокировки,,, блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки блокировки Arc blocking register, arc weight register, arc block register, first element AND, second element AND, OR element (RF Patent No. 2193796, cl. G06F 17/10, 7/38, publ. November 27, 2002, BI No. 33).

The disadvantage of this device is a narrow scope, due to the lack of search tools for lower bounds for placement in fully connected matrix systems (MS) with unidirectional information transfer according to the criterion of minimizing the intensity of the interaction of processes and data.

An object of the invention is to expand the scope of the device by introducing means of finding a lower estimate for placement in fully connected matrix systems with unidirectional information transfer according to the criterion of minimizing the intensity of the interaction of processes and data.

The technical problem is solved in that in a device for finding a lower estimate of placement in fully connected matrix systems for unidirectional information transfer (Fig. 1), containing a first shift register, a second shift register, a permutation formation unit (BFT), a permanent memory unit, a memory unit of the best option (BZLV), switch, ALU, arc selection decoder, reversible cell counter, RAM block, topology counter, first and second distance counters, multiplier, adder, register of minimum connection length, first element t comparisons, subtracter, start trigger, mode trigger, topology trigger, link length register, second comparison element, arc counter, arc lock decoder, arc number register, minimum weight register, electronic graph model, group 1 through n th OR elements, a group of 1st by mth AND elements, the first and second AND elements, the second block of OR elements, the third AND element, the first and second one-shots, the first, second and third delay elements, the first block of OR elements, the outputs of the BFP are connected to the corresponding inputs of the bl as a permanent memory and the corresponding inputs of the BZLV, the signaling output of the BFP is connected to the installation input of the start trigger, the outputs of the permanent memory block are connected to the corresponding inputs of the switch, the output of which is connected to the input of the ALU, the output of which is connected to the information input of the BZLV, and the output of the BZLV is connected to the first ALU information input, the shift register overflow output is connected to the shift register input, the outputs of the first and second shift registers from the first to the nth are connected to the first and second inputs of AND elements LI of the 1st through the nth, respectively, the shift register overflow output is connected to the ALU control input and the BFP control input, the device clock input is connected to the shift register input, the BFP clock input and the first inputs of the first and second elements AND, the counter output the arc is connected to the input of the arc selection decoder and the input of the arc number register data, the output of the block of elements OR is connected to the first input of the comparison element and to the data input of the minimum weight register, the output of the minimum weight register is connected to the second input of the cp element input and with the data input of the RAM block, the output of the delay element is connected to the input of setting the minimum weight register and to the input of setting the register of the arc number, the output of the third element And is connected to the sync input of the minimum weight register and to the sync input of the register of the arc number, the output of the arc number register is connected to the information input of the arc lock decoder, the overflow output of the arc counter is connected to the enable input of the arc lock decoder, as well as to the input of the delay element, the first counting input of the reverse the cell counter and the recording input of the RAM block, the output of the first element And is connected to the counting input of the arc counter and to the input of the delay element, the output of which is connected to the second input of the third element And, the first input of which is connected to the output of the comparison element, the second input of the first element And is connected with a direct output of the start trigger, which is also connected to the second input of the second element And, the third input of the first element And is connected to the inverse output of the mode trigger, the direct output of which is connected to the third input of the second AND element, the output of the second AND element is connected to the second counting input of the reversible cell counter, the output of which is connected to the address input of the RAM block, the output of which is connected to the first input of the multiplier, the output of the distance counter is connected to the second input of the multiplier, the output of which is connected to the first input the adder, the second input of which is connected to the output of the register of the minimum length of links and to the second input of the subtractor, the output of the adder is connected to the input of the register of the minimum length of links, the output of the element the holder is connected to the sync input of the register of the minimum length of the links, the output of the second AND element and the counting input of the distance counter are connected to the input of the third delay element, the output of the second one-shot is connected to the sync input of the distance counter, the overflow output of which is connected to the counting inputs of the topology counter, the distance meter and the input of the second single vibrator, the output of the topology counter is connected to the input of the distance counter, the data input of the device is connected to the data input of the topology counter, the sync input of the topology counter connected to the input of the device setup, the direct output of the topology job trigger is connected to the enable input of the topology counter, the installation input of the topology job trigger is connected to the device setup input, the reset input of the topology job trigger is connected to the device setup input, the overflow output of the reverse cell counter is connected to the trigger setup input mode, the reset input of which is connected to the installation input of the device, the output of the link length register is connected to the second input of the comparison element and to the first at the input of the subtractor, the first input of the comparison element is connected to the output of the ALU and the data input of the link length register, the output of a single vibrator is connected to the sync input of the link length register, the reset input of the trigger of the start of counting is connected to the device setup input, the lth output of the arc selection decoder (l = 1 , 2, ..., m) is connected to the lth input of the choice of the arc of the electronic graph model, the lth output of the arc lock decoder is connected to the lth input of the arc lock of the electronic graph model, the lth output of the weight of the arc of the electronic graph model is connected to l -th input of the block of elements OR and l- the input of the block of OR elements, the lth output of the element AND of the group of AND elements from the 1st to the mth is connected to the lth control input of the electronic model of the graph, the output of the block of OR elements is connected to the second information input of the ALU, the output of the comparison element is connected to the input of the first one-shot, the outputs of the elements from the 1st to the n-th OR are connected to the corresponding inputs of the elements of the 1st to the m-th, the output of the subtractor is connected to the output of the connection length of the device, an additional unit for generating a lower estimate containing the matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders, the first and second row counters, the first and second column counter, the matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) registers, the first and second decoders of horizontally fixed arcs, the first and second decoders of vertically fixed arcs, a matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR elements, the first and second matrices of ij ( i = 1, 2, ..., m; j = 1, 2, ..., n) AND elements, the first OR element, the RS inhibit trigger, the second OR element, the third and fourth row counter, the third incident vertex counter, the first and second element And, and the input of the device is connected n to the S-input of the RS-inhibit trigger, the R-input of which is connected to the overflow output of the first column counter, the direct output of the RS-inhibit inhibit is connected to the second input of the second element And, as well as to the first input of the first element And, the inverse output of the RS trigger prohibition is connected to the e-inputs of the third and fourth row counter, as well as the e-input of the third counter of the incident vertex, the c-input of which is connected to the overflow output of the third row counter and to the r-input of the fourth row counter, the output of the third incident counter The vertices are connected to the overflow output of the device, the clock input of the device is connected to the counting input of the fourth row counter, the input of which is connected to the direct output of the mode trigger, the overflow output of the fourth row counter is connected to the counting input of the third row counter and the counting input of the third counter of the incident vertex, the first the input of the second OR element is connected to the output of the first line counter, the overflow output of which is connected to the counting input of the second line counter, the overflow output of which dinene with enable inputs of the first and second column counter, the overflow output of which is connected to the counting input of the first column counter, the counting input of the second column counter is connected to the device clock input, the output of the second column counter is connected to the input of the second decoder of vertically fixed arcs, the output of the first column counter is connected with the input of the first decoder of vertically fixed arcs, the th input of the first line counter is connected to the output of the first element And, the second input of which is connected to by the direct output of the mode trigger, the device’s clock input is connected to the first input of the second AND element, the output of which is connected to the counting input of the first line counter, the output of the third line counter is connected to the first input of the first OR element, the second input of which is connected to the output of the third counter of the incident vertex, the third the input of the first OR element is connected to the output of the second row counter, the output of the first OR element is connected to the input of the first decoder of horizontally fixed arcs, the outputs from the first to the nth of which are connected with the corresponding second inputs of groups i.1, i.1, ..., i.1 (i = 1, 2, ..., m) of the elements of the second matrix from i.j (i = 1, 2, ..., m; j = 1, 2, ..., n) of AND elements, outputs from the first to the n-th second decoder of horizontally fixed arcs are connected to the corresponding first inputs of groups 1.j, 1.j, ..., 1.j (j = 1, 2 , ..., n) elements of the second matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, outputs from the first to the nth second 67 decoders of vertically fixed arcs are connected to the corresponding the second inputs of the groups 1.j, 1.j, ..., 17 (j = 1, 2, ..., n) of the elements of the first matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n ) And elements, the outputs from the first to the nth first decoder of vertically fixed arcs are connected to the corresponding m to the first inputs of groups i.1, i.1, ..., i.1 (i = 1, 2, ..., m) of the elements of the first matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements AND, the output of elements ij (i = 1, 2, ..., m; j = 1, 2, ..., n) And the first matrix of ij (i = 1, 2, ..., m; j = 1 , 2, ..., n) elements AND is connected to the first input of the element ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR matrices from ij (i = 1, 2, ..., m ; j = 1, 2, ..., n) elements OR, the corresponding second inputs of which are connected to the outputs of the elements ij (i = 1, 2, ..., m; j = 1, 2, ..., n) And the second matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, the outputs of the elements ij (i = 1, 2, ... , m; j = 1, 2, ..., n) OR matrices from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements OR are connected to the corresponding permitting inputs of the matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of registers whose outputs are connected to the corresponding first ij (i = 1, 2, ..., m; j = 1, 2, ..., n ) inputs of matrix elements from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders, to the second inputs of which the output of the RAM block is connected, outputs of elements ij (i = 1, 2, ... , m; j = 1, 2, ..., n) matrices from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders are connected to the corresponding To the existing D-inputs of the matrix from i.j (i = 1, 2, ..., m; j = 1, 2, ..., n) registers, the output of the fourth row counter is connected to the third input of the second 92 OR elements.

The electronic model of the graph contains m electronic models of the arc, and the l-th electronic model of the arc (l = 1, 2, ..., m) contains an arc lock trigger, an arc weight register, an arc lock register, the first AND element, the second AND element, the OR element moreover, the inputs of the first element And are connected to the corresponding inputs of the job graph of the device, the output of the first element And is connected to the sync input of the arc weight register and to the installation input of the arc lock trigger, the reset input of which is connected to the l-th input of the arc block of the electronic graph model, the data input is the arc weight histogram is connected to the l-th input of the device's arc weight, the first input of the OR element is connected to the l-th control input of the graph's electronic model, and the second input of the OR element is connected to the output of the second AND element, whose first input is connected to the direct output of the arc lock trigger and with the enabling input of the arc lock register, the second input of the second AND element is connected to the l-th input of the arc selection of the electronic graph model, the reset input of the arc lock register is connected to the l-th input of the device reset, the output of the arc lock register is connected to the l-th by the output of the arc weight of the electronic model of the graph, which is also connected to the output of the arc weight register, the output of the OR element is connected to the enable input of the arc weight register.

The invention is illustrated by drawings, where figure 1 shows a functional diagram of a device for finding a lower estimate of placement in a fully connected matrix systems (MS) for unidirectional transmission of information; figure 2 explains the essence of using an electronic model of the graph; figure 3 illustrates the principle of operation of the block 58 of the formation of the lower assessment in a fully connected MS with unidirectional transmission of information; figure 4. explains the principle of operation of the proposed device.

General features of the invention are as follows.

The proposed device can be used in the field of aircraft design, for example, when placing processes (algorithms, tasks, data, files, etc.). The device additionally allows you to search for lower estimates of placement in a fully connected MS with unidirectional information transfer.

, где

; w_ij - объем передаваемых данных между i-м и j-м процессорным модулем.The original task (process, algorithm, program) is represented as a directed weighted graph G = <X, E>, whose vertices x _i ∈X correspond to subproblems (subalgorithms, subprograms, etc.), and arcs e _ij ∈Е⊆Х × X define control and / or information links between subtasks and are actually data transmission channels. Graph G can be described by the adjacency matrix

where

; w _ij is the amount of data transmitted between the i-th and j-th processor module.

The MS is displayed by a homogeneous medium, which corresponds to the topological model in the form of the graph H = <U, V>, where

- множество модулей МС, организованных в матрицу

, где n является количеством модулей МС и количеством вершин графа G, V - множество межмодульных связей.

- a lot of MS modules organized into a matrix

, where n is the number of MS modules and the number of vertices of the graph G, V is the set of intermodular connections.

The placement of the graph G in the MS H will be set in the form of a map:

,

,

!Where

,

,

!

For the convenience of the further description, we assume that a homogeneous medium contains m × n elements, with m = n (where m and n are the number of processes). The functioning of a homogeneous environment is similar to the prototype. Upon receipt of a signal from an external control device (VUU), two vertices of the graph are rearranged and a new placement option is obtained. The proposed device calculates the values of the evaluation criteria and provides the specified values of the VUU. The latter analyzes the accepted values and either fixes the resulting placement as more optimal if the values of the criteria improve the previously found values, or ignore it.

The proposed device additionally implements a search for a lower estimate for the placement of weighted graphs in fully connected MSs with unidirectional information transfer according to the criterion of minimizing the intensity of interaction between processes and data.

The search principle of a lower placement estimate is illustrated in FIG. Here, FIG. 4a shows a hypothetical graph G of 9 vertices, and FIG. 4b shows the corresponding adjacency matrix W. FIGs. 4c, 4d show hypothetical options for placing graph arcs in the MS. MS modules are represented by squares, in the upper left corner of which their numbers are presented, dashed lines indicate the links of the MS modules, solid lines show hypothetical fixed arcs. When searching for a lower location estimate, it is assumed that the topologies of the original graph G and the graph of connections H between the modules are identical. That is, when calculating the lower bound, the arcs of the graph G with the greatest weight are assigned to the shortest routes in the graph H, not paying attention to the restrictions imposed by the actual relationships between the tasks. The resulting cumulative intensity value is the bottom placement estimate. In the case of a “real” placement option, its quality will be the better, as its total intensity value will be closer to the minimum lower estimate. Therefore, when placing tasks (algorithms, processes, data), it is necessary to strive for this value. It can be seen from FIG. 4g that this placement option is not a lower bound, since for example two arcs of the graph are assigned to modules 1-2 and 4-7 in it, which leads to an inevitable increase in the amount of data transfer between these modules. The placement option in FIG. 4c eliminates this problem and is at the same time a lower placement estimate. Minimizing the total amount of data transferred is important to reduce the overall time taken to complete the task. Therefore, when designing a device, it is actually necessary to look at the adjacency matrix of graph G, not paying attention to communications, and sequentially assign arcs to the modules of matrix N.

The device for finding a lower estimate of placement in fully-connected matrix systems for unidirectional information transfer (Fig. 1) contains a first shift register 1, a second shift register 2, a permutation formation unit (BFT) 3, a permanent memory unit 4, a best option memory unit 5 (LSS) , switch 6, ALU 7, decoder 8 for arc selection, reversible counter 9 cells, block 10 RAM, counter 11 topology, first 12 and second 13 distance counters, multiplier 14, adder 15, register 16 of the minimum connection length, the first comparison element 17 subtract Atelier 18, trigger 19 of the beginning of the count, trigger 23 of the mode, trigger 24 of the job topology, register 25 links length, the second element 26 comparison, counter 27 arcs, decoder 28 lock arc, register 29 of the arc number, register 30 of the minimum weight, electronic model 31 columns , a group of elements OR 32.1-32.n, a group of elements AND 33.1-33.m, the first 34 and second 35 elements AND, the second block of elements OR 36, the third element AND 37, the first 41 and second 42 single vibrators, the first 43, the second 44 and the third 45 delay elements, the first block of OR elements 46, and the outputs of the BFP 3 are connected to the corresponding inputs DAM block 4 and the corresponding inputs BZLV 5, the signaling output of the BFP 3 is connected to the installation input of the trigger 19 start counting, the outputs of the block 4 of constant memory are connected to the corresponding inputs of the switch 6, the output of which is connected to the input of the ALU 7, the output of which is connected to the information input BZLV 5, and the output of BZLV 5 is connected to the first information input of ALU 7, the overflow output of shift register 1 is connected to the input of shift register 2, the outputs of registers 1 and 2 from the first to the nth are connected to the first and second inputs of AND elements LI 32.1-32.n, respectively, the overflow output of the shift register 2 is connected to the control input of the ALU 7 and to the control input of the BFP 3, the clock input 57 of the device is connected to the input of the shift register 1, with the clock input of the BFP 3 and to the first inputs of the elements And 34 and 35, the output of the counter 27 of the arcs is connected to the input of the decoder 8 of the arc selection and the data input of the register 29 of the arc number, the output of the block of elements OR 36 is connected to the first input of the element 17 of the comparison and to the data input of the register 30 of the minimum weight, the output of the register 30 of the minimum weight is connected to the second input element 17 for comparison with the data input of the RAM block 10, the output of the delay element 43 is connected to the input of the installation of the register 30 of the minimum weight and to the input of the installation of the register 29 of the arc number, the output of the third element And 37 is connected to the clock input of the register 30 of the minimum weight and to the clock input of the register 29 of the arc number , the output of the register 29 of the arc number is connected to the information input of the arc lock decoder 28, the overflow output of the arc counter 27 is connected to the enable input of the arc lock decoder 28, as well as the input of the delay element 43, the first by the input of the reversible counter of 9 cells and the recording input of the main memory unit 10, the output of the And 34 element is connected to the counting input of the arc counter 27 and to the input of the delay element 44, the output of which is connected to the second input of the And 37 element, the first input of which is connected to the output of the element 17 for comparison, the second input of the And 34 element is connected to the direct output of the trigger of the start of counting, which is also connected to the second input of the And 35 element, the third input of the And 34 element is connected to the inverse output of the trigger 23 of the mode, the direct output of which is connected to the third electronic input I 35, the output of the And 35 element is connected to the second counting input of the reversible counter 9 cells, the output of which is connected to the address input of the RAM block 10, the output of which is connected to the first input of the multiplier 14, the output of the distance meter 13 is connected to the second input of the multiplier 14, the output which is connected to the first input of the adder 15, the second input of which is connected to the output of the register 16 of the minimum connection length and to the second input of the subtractor 18, the output of the adder 15 is connected to the input of the register 16 of the minimum connection length, the output of the element 45 delay connected to the synchro input of register 16 of the minimum connection length, the output of the And 35 element and the counting input of the distance meter 12 are connected to the input of the delay element 45, the output of the one-shot 42 is connected to the clock input of the distance meter 12, the overflow output of which is connected to the counting inputs of the counter 11 of the topology 13 distances to the input of the one-shot 42, the output of the counter 11 of the topology is connected to the input of the counter 12 distances, the input 51 of the device data is connected to the data input of the counter 11 of the topology, the sync input of the counter of 11 topology is connected It is connected to the input 52 of the device setup, the direct output of the trigger 24 of the topology job is connected to the enable input of the topology counter 11, the installation input of the trigger 24 of the topology job is connected to the input 49 of the device setup, the reset input of the trigger 24 of the topology job is connected to the device setup input 50, the overflow output is reversible a counter of 9 cells is connected to the installation input of the mode trigger 23, the reset input of which is connected to the device installation input 48, the output of the link length register 25 is connected to the second input of the element 26 is compared I’m connected to the first input of the subtractor 18, the first input of the comparison element 26 is connected to the ALU 7 output and the data input of the link length register 25, the output of the single vibrator 41 is connected to the sync input of the link length 25 register, the reset input of the trigger 19 of the count start is connected to the device installation input 47, The lth output of the arc selection decoder 8 (l = 1, 2, ..., m) is connected to the lth input of the choice of the arc of the electronic model 31 of the graph, the lth output of decoder 28 of the arc lock is connected to the lth input of the arc lock of the electronic model 31 columns, the l-th output of the weight of the arc of the electronic model 31 of the graph is connected to l- the input of the OR block of elements 36 and the lth input of the block of OR elements 46, the output of the AND 33.l element is connected to the l-th control input of the graph's electronic model 31, the output of the block of OR elements 46 is connected to the second information input of the ALU 7, the output of the element 26 the comparison is connected to the input of the one-shot 41, the outputs of the elements OR 32.1-32.n are connected to the corresponding inputs of the elements AND 33.1-33.m, the output of the subtractor 18 is connected to the output 53 of the device connection length, as well as an additionally introduced lower evaluation unit 58 containing the matrix 59.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders, the first 71 and second 60 row counters, the first 61 and second 62 column counts, the matrix 63.ij (i = 1, 2, ..., m; j = 1, 2, ... , n) registers, first 64 and second 65 decoders of horizontally fixed arcs, first 66 and second 67 decoders of vertically fixed arcs, matrix 68.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR elements, the first 69.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) and the second 70. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) the matrix of AND elements, the first 78 OR element, the RS inhibit trigger 79, the second 92 OR element, the third 80 and fourth 81 line counts, the third 82 incident peak counter, the first 89 and second th 90th element And, and the input 75 of the device is connected to the S-input of the RS-trigger 79 of the ban, the R-input of which is connected to the overflow output of the first 61 column counter, the direct output of the RS-trigger 79 of the ban is connected to the second input of the second 90 of the element And also to the first input of the first 89 AND element, the inverse output of the RS-trigger 79 of the ban is connected to the e-inputs of the third 80 and fourth 81 line counts, as well as to the e-input of the third 82 counter of the incident vertex, the c-input of which is connected to the overflow output of the third 80 line counter and to the r-input of the fourth 81 s line counter, the overflow output of the third 82 counter of the incident vertex is connected to the overflow output 93 of the device, the clock 57 of the device input is connected to the counting input of the fourth 81 line counter, the input of which is connected to the direct output of the mode trigger 23, the overflow output of the fourth 81 line counter is connected to the counting input of the third 80 line counter and the counting input of the third 82 counter of the incident vertex, the first input of the second 92 OR element is connected to the output of the first 71 line counter, the overflow output of which connected to the counting input of the second 60 line counter, the overflow output of which is connected to the enable inputs of the first 61 and second 62 column counters, the overflow output of which is connected to the counting input of the first 61 column counters, the counting input of the second 62 column counter is connected to the clock 57 of the device input, output the second 62 column counter is connected to the input of the second 67 decoder of vertically fixed arcs, the output of the first 61 column counter is connected to the input of the first 66 decoder of vertically fixed arcs One of the first 71 line counters is connected to the output of the first 89 AND element, the second input of which is connected to the direct output of the mode trigger 23, clock 57 device input is connected to the first input of the second 90 AND element, the output of which is connected to the counting input of the first 71 line counter, the output of the third 80 line counter is connected to the first input of the first 78 OR element, the second input of which is connected to the output of the third 82 counter of the incident vertex, the third input of the first 78 OR element is connected to the output of the second 60 line counter, the output of the first 78 AND element LI is connected to the input of the first 64 decoder of horizontally fixed arcs, the outputs from the first to the nth of which are connected to the corresponding second inputs of the groups (70.1.1, 70.2.1, ..., 70.m.1), (70.2.1, 70.2. 2, ..., 70.m.2), ..., (70.m.1, 70.m.2, ..., 70.mn) the second 70.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) the matrix of elements And, the outputs from the first to the nth second 65 of the decoder of horizontally fixed arcs are connected to the corresponding first inputs of the groups (70.1.1, 70.1.2, ..., 70.1.n), ( 70.2.1, 70.2.2, ..., 70.2.n), ..., (70.m.1, 70.m.2, ..., 70.mn) the second 70.ij (i = 1, 2, ..., m ; j = 1, 2, ..., n) the matrix of elements And, the outputs from the first to the nth second 67 of the decoder of vertically fixed arcs are connected to the corresponding second inputs of the groups (69.1.1, 69.1.2, ..., 69.1.n), (69.2.1, 69.2.2, ..., 69.2.n), ..., (69.m.1, 69.m.2, ..., 69.mn) elements of the first 69.ij (i = 1, 2, ... , m; j = 1, 2, ..., n) matrix of elements And, outputs from the first to the nth first 66 decipher an ator of vertically fixed arcs is connected to the corresponding first inputs of the groups (69.1.1, 69.2.1, ..., 69.m.1), (69.2.1, 69.2.2, ..., 69.m.2), ..., (69 .m.1, 69.m.2, ..., 69.mn) of the elements of the first 69.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the matrix of elements And, the output of elements 69 .ij (i = 1, 2, ..., m; j = 1, 2, ..., n) and the first 69. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) matrices elements And is connected to the first input of element 68. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR matrix 68. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR elements, the corresponding second inputs of which are connected to the outputs of elements 70.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) And the second 70. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) matrix elements AND , outputs of the elements 68.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR matrices 68. ij (i = 1, 2, ..., m; j = 1, 2, ... , n) of the OR elements are connected to the corresponding resolving ith inputs 63.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the matrix 63. ij (i = 1, 2, ..., m ; j = 1, 2, ..., n) of registers whose outputs are connected to the corresponding first inputs of elements 59. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the matrix 59.ij ( i = 1, 2, ..., m; j = 1, 2, ..., n) adders The input of which is connected to the output of RAM block 10, the outputs of the elements 59.ij (i = 1, 2, ... m; j = 1, 2, ..., n; matrices 59. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders are connected to the corresponding D-inputs of the matrix 63.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) registers, the output of the fourth 81 line counts are connected with the third input of the second 92 element OR.

The electronic model 31 of the graph (Fig. 2) contains m electronic models of the arc, and the electronic model 31.l of the arc (l = 1, 2, ..., m) contains a trigger 20.l of blocking the arc, register 21.l of the weight of the arc, register 22 .l arc locks, the first AND 38.l element, the second AND 39.l element, the OR 40.l element, and the inputs of the AND 38.l element are connected to the corresponding inputs of the device graph (where y and z are the numbers of the start and end vertices of the lth arc of the graph, respectively), the output of AND 38.l is connected to the clock input of the register 21.l of the arc weight and to the installation input of the trigger 20.l of the lock d gi, the reset input of which is connected to the l-th input of blocking the arc of model 31, the data input of the register 21.l of the weight of the arc is connected to the input 54.l of the weight of the arc of the device, the first input of the OR 40.l element is connected to the l-th control input of the model 31 and the second input of the OR element 40.l is connected to the output of the AND 39.l element, the first input of which is connected to the direct output of the arc lock trigger 20.l and with the enable input of the arc lock register 22.l, the second input of the AND 39.l element is connected with the l-th input of the arc selection model 31, the reset input of the lock register 22.l is connected to the reset input 55.l device, the output of the arc lock register 22.l is connected to the l-th output of the arc weight model 31, which is also connected to the output of the arc weight register 21.l, the output of the OR 40.l element is connected to the enable input of the arc weight register 21.l.

The purpose of the elements and blocks of the search device for the lower allocation estimate in fully connected matrix systems with unidirectional information transfer (Fig. 1) is as follows.

The first and second shift registers 1 and 2 are necessary to implement sequential enumeration of pairs of vertices of the digraph G.

Block 3 of the formation of permutations enumerates all possible locations of the vertices of the graph G at the positions of the given topological model.

The read-only memory unit 4 stores binary codes of item numbers.

Block 5 memorizing the best option is used to memorize the currently best accommodation options.

Switch 6 provides sequential write-off from block 4 of codes of numbers of selected positions for transferring them to ALU 7.

The arithmetic-logic device 7 is necessary to determine the distance between the positions at which the selected vertices of the graph are placed, and to calculate the bond length L for the formed placement option. This device is capable of determining distances between positions for both weighted graphs and unweighted graphs.

The decoder 8 of the arc selection together with the counter 27 of the arcs are designed to select from the EMG 31 of the arc with the number recorded in the counter 27.

The reversible counter of 9 cells serves to organize sequential enumeration of the addresses of the block 10 of the RAM in the direct and reverse order, respectively, when recording information and reading it.

The RAM block 10 serves to store the weights w _{i, j of the} arcs of the digraph G in ascending order of their values.

с заданным значением (для кольцевой топологической модели общее число таких элементов постоянно и составляет n, для линейной это число уменьшается от n-1 для

до 1 для

) (на фиг.1 не показан).The counter 11 topology is necessary for counting and transmitting to the counter 12 the number of processed elements of the vector

with a given value (for a ring topological model, the total number of such elements is constant and is n, for a linear one this number decreases from n-1 for

up to 1 for

) (not shown in FIG. 1).

) (на фиг.1 не показан).The first counter 12 distances and the second counter 13 distances are designed to organize sorting in increasing order of nonzero elements of the matrix of distances D (thus, at the output of counter 13, a vector

) (not shown in FIG. 1).

) из счетчика 13 расстояний (на фиг.1 не показан).The multiplier 14 is necessary to multiply the weight of the arc from the block 10 of RAM by the distance between the positions of the topological model (vector element

) from the counter 13 distances (figure 1 is not shown).

The adder 15 is designed to sum the values from the multiplier 14 and the register 16 (not shown in figure 1).

The register 16 of the minimum bond length stores the value of the minimum possible bond length L ^∗ for a given graph (not shown in FIG. 1).

The first comparison element 17 is used to compare the weight of the current arc with the least weight currently recorded in the register 30.

The subtractor 18 serves to find the degree of optimality of the placement ξ by the formula (2). The value of L ^∗ comes from the output of the register 16 of the minimum length of bonds, L comes from the output of the register 25 of the length of bonds (not shown in Fig. 1).

The trigger 19 of the beginning of the account is used to indicate the transition from the mode of formation formation in the mode of its evaluation.

The trigger 23 mode is used to store a sign of the current operation. If the trigger 23 is set to zero, this means writing the weights of the arcs in increasing order to the RAM block 10, and to one, finding the minimum possible length L ^* according to formula (1).

The trigger 24 for setting the topology is intended to set the type of the topological model: if trigger 24 is set to one, this means choosing a linear model, zero means a ring model (not shown in Fig. 1).

The bond length register 25 is intended to store the value of the bond length L for the best placement option stored in the BZLV 5 (not shown in FIG. 1).

The second comparison element 26 is intended to compare the values of the bond length L of the currently best placement option from register 25 with the current bond length (not shown in FIG.

The decoder 28 of the arc lock is designed to select the arc that you want to block in the current cycle of the device.

The arc number register 29 is used to store the arc number with the minimum weight selected in the current cycle of the device.

The minimum weight register 30 is needed to store the value of the currently minimum arc weight.

The group of elements OR 32.1-32.n is necessary to combine the corresponding signals from registers 1 and 2.

The group of elements AND 33.1-33.m is designed to select the corresponding arcs of the graph G according to the signals from the elements OR 32.1-32.n.

The first and second elements And 34 and 35 are necessary to block the transmission of pulses from the clock input 57 of the device to the elements and blocks that ensure the ordering of the weights of the graph arcs in block 10 and the calculation of the values of the bond length L ^∗, respectively.

The second block of OR elements 36 is necessary to connect the weight of the current arc to the comparison element 17 and the register 30.

The third element And 37 is designed to block the passage of pulses to the synchronization inputs of registers 29 and 30.

The electronic model 31 of the graph is used to simulate the topology of graph G representing the hosted object.

The purpose of the elements of the block 58 forming the lower score (figure 3) is as follows.

Matrix 59.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the adders is intended for summing and subsequent recording in the corresponding matrix 63. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) registers of codes of intensity values of arcs assigned to the corresponding pairs of processors.

The first 61 and second 62 column counters are used to store the row and column numbers in which the arcs of column G will be fixed in the MS columns.

The matrix 63.i.j (i = 1, 2, ..., m; j = 1, 2, ..., n) of the registers is designed to store the total codes of the intensity values of the arcs assigned to this pair of processors in the rows and columns of the MS.

The first 64 and second 65 decoders of horizontally fixed arcs are needed to select the processor in which the arc of graph G will be fixed. The choice is made taking into account that the arcs are initially fixed horizontally in the MS.

The first 66 and second 67 decoders vertically fixed arcs are used to select the processor, and taking into account the fact that the arcs are fixed vertically, but only after the initial horizontal fixation.

The matrix 68.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the OR elements serves to combine the signals from the outputs of the corresponding elements of the first 69. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) and the second 70.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of the matrix of elements And followed by supplying the matrix 63.ij ( i = 1, 2, ..., m; j = 1, 2, ..., n) registers.

The first 69.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) and the second 70.ij (ij (i = 1, 2, ..., m; j = 1, 2, ... , n) the matrix of AND elements is intended for combining signals with the subsequent supply to the corresponding inputs 68.ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of OR elements and its further arrival at the corresponding enabling inputs th matrix 63. ij (i = 1, 2, ..., m; j = 1, 2, ..., n) registers.

The first 71 and second 60 row counters are used to store the number of the corresponding row and column necessary to select a pair of processors designed to fix the next arc of column G in the MS lines.

The input 75 of the device is designed to supply a single pulse to the S-input to the RS-trigger 79 of the ban to set it in a single state.

The first 78 OR elements are necessary for passing codes to the input of the second 67 decoder of vertically fixed arcs, as well as to the input of the first 64 decoders of horizontally fixed arcs, respectively.

The RS-trigger 79 prohibition is used to select the operating mode of the device. When it is in a single state, fixing is performed in the rows and columns of the MS. If the RS flip-flop 79 is in the zero state, then fixation is performed in the MS diagonals (for example, in Figs. 4c and 4d these are modules 1-5, 2-4, etc.).

The third 80 and fourth 81 line counts are used to store the corresponding pair of processor modules into which the arc of graph G will be fixed. The arc is fixed in the diagonal of the MS. For example, in FIG. 4c, these are pairs of processor modules 2-4, 5-7, 3-5, 6-8.

The third 82 counter of the incident vertex is designed to store the code of the vertex incident to the currently selected arc of the graph G to be fixed.

The first 89 and second 90 element And is designed to prohibit the passage of signals from the outputs of the block 10 of RAM and the direct output of the trigger 79 prohibition.

The second 92 OR element is used to supply signals from the outputs of the first 71 line counter and the fourth 81 line counter to the input of the second 65 decoder of horizontally fixed arcs.

The output 93 of the overflow of the device serves to supply to the VUU a signal about the overflow of the third 82 counter of the incident vertex, which simultaneously means the completion of the device.

Consider the operation of the proposed device.

Initially, registers 29, 30 contain the values "11 ... 1". Counters 27, 9 contain a zero code. Triggers 19 and 23 are in a state of logical zero. Triggers 20.l of model 31.l, l = 1, 2, ..., m, are either in the state of a logical unit or in a state of logical zero (which is determined respectively by the presence or absence of the l-th arc in the graph). Registers 21.l contain either the values of the weights of the corresponding arcs or zero codes (if the corresponding arcs are absent in the original graph). If a graph with unweighted arcs is placed, then the registers 21.l contain either the codes “00 ... 01” or zero codes. Information about the placed graph is recorded by applying combinations of signals to the inputs 56.1-56.n of the device and the weights of the arcs to the inputs 54.l of the device. The appearance of single signals at the inputs 56.i-1 and 56.i means the presence in the graph of the arc e _{i-1, i} (the weight of this arc is fed to the input 54 of the corresponding model of the arc). A counter zero is set in counter 71, a two-digit code ("0 ... 10") in counter 60, a zero code ("0 ... 00") in counter 62. The counter 61 stores the unit code ("0 ... 01"). Counter 81 stores the zero code, counter 80 stores the deuce code ("0 ... 010"), counter 82 stores the deuce code.

The proposed device is capable of solving the following problems: placing unweighted graphs in a linear topological model, placing weighted graphs in a linear and ring model, and assessing the degree of proximity of the generated arrangement to the optimal one. Additionally, the proposed device allows you to search for a lower estimate of the placement of weighted graphs in fully connected MS with unidirectional information transfer according to the criterion of minimizing the intensity of the interaction of processes and data.

The task of placing unweighted graphs with a topological model in the form of a ruler is solved in the device similarly to the prototype. In this case, only the so-called “upper” part of the circuit works, which includes the EMG 31, registers 1 and 2, the group of elements OR 32.1-32.n, the group of elements AND 33.1-31.m, the block of elements OR 46, register 25, comparison element 26, one-shot 41, as well as BFP 3, read-only memory unit 4, BZLV 5, switch 6 and ALU 7.

. Одновременно в АЛУ 7 происходит и накопление суммарной длины связей L. Подсчет суммарной длины связей для текущего варианта размещения завершается, когда на выходе переполнения регистра 2 появляется сигнал переполнения. Одновременно этот же сигнал поступает на БФП 3, подготавливая его к формированию новой перестановки.Register 1 and register 2 sequentially select pairs of vertices as pulses arrive from input 57 of the device. The signals of the selected pair of vertices pass through two corresponding elements of the group of elements OR 32.1-32.n and then form a single signal at the output of the corresponding element AND of group 33.1-33.m (let's say element 33.l). A single signal from the AND 33.l element is supplied to the OR 40.l element (arc models 31.l) and, further getting to the enable input (s) of the register 21.l, thereby resolves the appearance of data (the weight of the l-th arc) on output of this register. Since the placed graph is unweighted, register 21.l contains either the code “00 ... 01” or the code “00 ... 00” (no arc). We consider this code to be nonzero. The code "00 ... 01" from the output of the register 21.l goes to the block of OR elements 46 and then through it to the ALU 7. At the same time, the block 3 of the formation of permutations determines the positions for the selected vertices, and ALU 7 generates a command for determining the distance between positions in which to place the selected vertices of the graph. This distance is determined by the formula

. At the same time, in ALU 7, the accumulation of the total length of the bonds L occurs. The calculation of the total length of the bonds for the current placement option is completed when an overflow signal appears at the output of the overflow of register 2. At the same time, the same signal arrives at BFP 3, preparing it for the formation of a new permutation.

The permutations are formed in the spatiotemporal form, that is, at each clock moment, a single signal is initiated only at one (qth) output of the BFP 3, and their sequence determines the corresponding permutation. For example, a permutation (3 1 2) means that the first clock pulse appears at the second output of the BFP, the second at the third, the third at the first. In accordance with this, from the unit 4 of the permanent memory (into the unit 4 of the permanent memory, binary codes of the position numbers are entered) through the switch 6, the codes of the second position, third and first will be sequentially written off to ALU 7. This, in turn, means that the first vertex is placed in the second position, the second in the third and the third in the first. The best placement option is written in block 5 and the corresponding value of the bond length L is registered in register 25. The appearance of a signal at the signaling output of the BFP 3 indicates that all permutations are formed, and the best placement option is fixed in BZLV 5.

The problem of placing weighted and unweighted graphs in linear and / or ring topological models, as well as the problem of assessing the degree of closeness of the formed arrangement to the optimal one, is solved as in the prototype and therefore is not considered here.

The task of assessing the degree of closeness of the formed arrangement to the optimal one is solved as follows (in this case, only the “lower” part of the circuit works, including decoders 8 and 28, comparison element 17, counters 27, 9, 11, 12 and 13, RAM block 10, registers 16, 25, 29 and 30, triggers 19, 23 and 24, multiplier 14, adder 15, subtractor 18, block of OR elements 36, AND elements 34, 35 and 37, delay elements 43, 44 and 45 and one-shot 42).

When a single signal appears on the signaling output of the BFP 3, trigger 19 is set to unity. A single signal from the direct output of the trigger 19 is supplied to the second inputs of the And 34 element and the And 35 element. Since the mode trigger 23 is in the zero state, the element 35 remains closed and the element 34 is opened for the passage of clock pulses.

The first clock pulse passes through the And 34 element, from where this pulse arrives at the counting input of the counter 27 and sets the value “00 ... 01” with a rising edge. The code from the output of the counter 27 goes to the input of the register data 29 and to the input of the decoder 8, initiating the appearance of a unit at its first output. This unit goes to the second input of the And 39.1 element (models 31.1). If one is present at the first input of element 39.1 (trigger 20.1 is in a single state), then at the output of element 39.1 a single signal for selecting an arc appears. From the output of the AND 39.1 element, this signal passes through the OR 40.1 element, goes to the enable input of the register 21.1, and opens its output. As a result, the weight of the arc from register 21.1 passes through the block of OR elements 36, from where it enters the first input of the comparison element 17, at the second input of which there is a code from register 30 (initially “11 ... 1”). If the code from the block of elements OR 36 (weight of the selected arc) is less than that already existing in the register 30, a single signal is generated at the output of element 17. This single signal is supplied to the first input of the And 37 element and ensures the passage of a clock pulse from the And 34 element delayed by the delay element 44. The pulse from the And 37 element is supplied to the sync inputs of the register 29 and the register 30 and records the value from the output of the counter 27 (current arc number) and the weight code of the selected arc from block 36 (as the minimum at the moment), respectively, on the rising edge. If there is zero at the output of element 17, the AND element 37 is blocked and therefore the pulse from the delay element 44 does not arrive at the clock inputs of the registers 29 and 30.

The next clock pulse likewise passes through the And 34 element, again enters the counting input of the counter 27 and increases the value of this counter to "00 ... 010". From the output of the counter 27, the code again falls onto the decoder 8, which causes a unit to appear at its second output. This unit likewise enters the weighted arc model 31.2, and from the second output of the arc weight of model 31, the weight code of the second arc is sent to the block of elements OR 36. If such an arc exists, then the corresponding code falls on the first input of the comparison element 17, the second input of which comes from register 30, the weight recorded in the previous steps. If the new weight is less than the previous one, then a single signal indicating this is supplied to the first input of the And 37 element and passes through it a pulse from the delay element 44. From the output of the And 37 element, the pulse again goes to the sync inputs of the registers 29 and 30 and writes the new arc weight (the weight of the second arc) to the register 30 at the front input, and in the register 29 the counter value 27 as the number of the arc with the least weight at the moment.

This happens until an overflow signal (impulse) appears on the overflow output of counter 27, signaling that all arcs are scanned and the smallest weight is in register 30, and the corresponding arc number is in register 29. In this case, counter 27 is reset to the zero state, and the overflow signal is simultaneously fed to the recording input of the RAM unit 10 to the delay element 43 and the first counting input of the counter 9. At the trailing edge of the overflow signal, the counter 9 increases its value to “00 ... 01”. As a result, the minimum weight of the arc from register 30 is entered into the RAM block 10 at the address “00 ... 01”. The overflow signal from the counter 27 is simultaneously fed to the enable input of the decoder 28, providing a choice of its output depending on the code supplied from the output of the register 29. The signal from the selected output of the decoder 28 (for example, the l-th) is fed to the reset input of the trigger 20.l of model 31.l, setting it to zero (blocking of the l-th arc for the next cycles of the device is provided). By the time the minimum weight of the arc is already recorded in the block 10 of RAM, the overflow signal from the output of the delay element 43 is supplied to the installation inputs (S) of the registers 29 and 30 and sets these registers to the initial state "11 ... 1". The current cycle of the device ends.

The next pulse passing through the element And 34, makes the device work again according to the above algorithm. In register 30, the smallest weight of the arc is stored without considering the arcs blocked in previous cycles. When the decoder 8 selects an unblocked arc, the device operates as described above. When the decoder 8 selects an already blocked arc, the signal from the output of the decoder 8 does not pass through the AND 39.l element (there is a zero on the direct output of the trigger 20.l). At the same time, the signal from the direct output of the trigger 20.l goes to the enable input of the register 22.l. As a result, the null code (written to this register from the input 55.l) from the output of the register 22.l enters through the block of elements OR 36 to the first input of the comparison element 17 and, being obviously smaller than any other code located in the register 30, provides a zero signal at the output of element 17 and blocking element 37.

When the overflow signal reappears on counter 27, the counter 9 increases to the code “00 ... 010”. The overflow signal is fed to the recording input of the block 10 of the RAM and writes the code of the arc weight from the output of the register 30 from the counter 9 to the address “00 ... 010”. Thus, the block weights in the memory 10 of the arcs of the graph G are sequentially written in ascending order of the corresponding values . This happens until the counter 9 generates an overflow signal. This signal is fed to the installation S-input of the trigger 23, sets it to unity and thereby allows the passage of clock pulses through the And 35 element, prohibiting their passage through the And 34 element. The counter 9 itself is reversed from summing to subtracting. From this moment, the search begins for a lower estimate of placement in matrix systems with directional information transfer. The task of calculating the minimum possible length L ^* is solved in the same way as in the prototype and therefore is not considered here.

The task of finding a lower estimate of placement in fully connected matrix systems with unidirectional information transfer is solved in the proposed device as follows.

Initially, similar to the principle described above, the “upper part” of the circuit is “worked out” so that in block 10 of the main memory there are arcs of graph G arranged in decreasing order of their weights (Fig. 1). As can be seen from figure 4, when assigning arcs to the processors of the matrix system, you should first assign arcs with the highest values of weights. Therefore, when choosing from block 10 of RAM, the first selected arc will be the arc with the highest weight value, and the last with the smallest.

The first clock pulse from the input 57 of the device is supplied to the counting input of the counter 62, to the first inputs of the elements 90 and 35 I. As a result, the pulse passes to the subtracting input of the reverse counter 9 and decreases the value by one on the rising edge. As a result, the resulting code is fed to the address input A of the RAM block 10 and the value of the arc weight with the maximum weight appears on the output. Counter 62 is closed, since no single signal is present at its enable input. Since at the second input of the 90 And element there is a unit potential from the direct output of the trigger 79, the unit signal passes to the counting input of the counter 71. At its resolution input, there is a unit potential, since there is a unit signal at the two inputs of the 89 And element, and therefore, at its output is a unit. Therefore, on the rising edge, the counter 71 is incremented by one to the unit code ("0 ... 01"). The unit code passes through the OR element 92 and is fed to the input of the decoder 65. Therefore, a single signal appears on its first output, which is fed to the first inputs of the elements 70.1.1, 70.1.2, ..., 70.1.n I. At this point, from the counter output 60, the code of the number two, passing through the element 78 OR entered the input of the decoder 64. Since the code of the number two is present at the input of the decoder 64, a single pulse appears at its second output, which is fed to the second inputs of the elements 70.1.2, 70.2.2, ... , 70.m.2 I. Thus, on the two inputs of the element 70.1.2 And single signals appear ly, whereby at its output a single pulse appears which is supplied to the second input of OR 68.1.2 and further enabling input th register 63.1.2. As a result, the code stored in the register 63.1.2 is fed to the first input of the adder 59.1.2. At this point, at its second input, the weight of the arc from the output of block 10 of the RAM is present. As a result of summation, the resulting number is fed to the D-input of register 63.1.2 and stored there. Thus, the intensity value of the first arc of column G in the MS is fixed (for example, in Fig. 4c this is the arc from module 1 to module 2 of the MS).

The next clock pulse comes from input 57 to the inputs of element 35 AND, to the counting input of counter 62 and the first input of element 90 I. As a result, the value stored in the reverse counter 9 decreases by one, and the value stored in it is supplied to address input A block 10 of RAM. Therefore, the next code for the weight of the arc of graph G appears at its output. Counter 62 is closed due to the lack of a signal at the input o. The unit potential from the direct output of the trigger 23 is supplied to the second input of the 89 I element. Since there is a unit from the direct output of the trigger 79 at its first input, a single signal appears at the input of the counter 71. As a result of this, a single impulse received at the counting input of the counter 71 increases its content by one to a two-digit code (“0 ... 010”). This code through the OR element 92 is fed to the input of the decoder 65 and a single signal appears on its second output, which is fed to the first inputs of the elements 70.2.1, 70.2.2, ..., 70.2.n I. By this time, the counter 60 is still stored the value of the code is two. This code passes to the first input of the OR element 78 and then to the input of the decoder 64. As a result, a single signal appears on its second output, which is fed to the second inputs of the elements 70.1.2, 70.2.2, ..., 70.m.2 I. В As a result, on both inputs of the element 70.2.2 And single signals appear. As a result, at its output, a unit appears at the permissive input of the 63.2.2 register. The code stored in it appears, which goes to the first input of the adder 63.2.2, at the second input of which there is a code for the weight of the arc of column G from the output of block 10 of RAM. As a result, the total value is received for writing to the D-input of register 63.2.2. Thus, the second arc of the graph G is fixed.

This continues until an overflow signal appears at the overflow output of the counter 71. This means that the fixation in the first "column" of MS lines is completed and it is necessary to continue fixing in the second "column" of MS lines. The overflow signal from the overflow output of the counter 71 is fed to the counting input of the counter 60, setting the code of the number three ("0 ... 011") in it. Counter 71 is reset to unit code.

Further, the work continues similarly to the principle described above until a single pulse appears at the output of the overflow of the counter 60. This means that the fixation of the arcs of graph G in the horizontal orientation of the MS is completed. For example, in Fig. 4c, these are arcs fixed in modules MS 1-2, 4-5, 7-8, 2-3, 5-6, 8-9. Therefore, further fixation of the arcs in the vertical orientation of the MS is necessary. The pulse from the overflow output of the counter 60 enters the enable inputs of the counters 61 and 62, allowing their operation.

The next clock pulse is fed to the input of the 35 And element, to the counting input of the counter 62. Due to the supply of the pulse to the input of the 35 And element, the new value of the arc weight of the graph G from the output of the main memory unit 10 goes to the lower evaluation unit 58. The same clock pulse received at the counting input of the counter 62 increases the code contained in it by one and sets the code of the unit in it. The unit code from the output of the counter 62 is fed to the input of the decoder 67. Since the unit code was supplied to the input of the decoder 67, a single pulse is excited at its first output, which is fed to the second inputs of the elements 69.1.1, 69.1.2, ..., 69.1.n The unit code from the output of the counter 61 goes to the first input of the OR element 91, and passing through it further the input of the decoder 66, as a result of which a single pulse appears at its first output, which goes to the first inputs of the elements 69.1.1, 69.2.1, ... , 69.m.1 I. As a result of this, on both inputs of the element 69.1.1 And one appears primary signals, which means that a single signal is initiated at its output, which passes to the first input of OR element 68.1.1 and then to the permissive input of register 63.1.1. As a result of this, the value from its output goes to the first input of the adder 59.1.1, at the second output of which there is a code for the weight of the arc of column G from the output of block 10 of RAM. The total value from the output of the adder 59.1.1 goes to the D-input of the register 63.1.1 and is written there. Thus, the arc of the graph G is recorded in vertical orientation in the MS. For example, in FIG. 4c, this is an arc fixed in modules 1-4.

The next clock pulse arrives at the counting input of the counter 62 and on the rising edge increases their contents by the leading edge by one to a deuce code in the counter 62. The code of the number two from the output of the counter 62 goes to the input of the decoder 67. A single signal appears at the second output of the decoder 67, which is fed to the second inputs of the elements 69.2.1, 69.2.2, ..., 69.2.n I. The unit code from the output of the counter 61 is fed to the input of the decoder 66, at the first output of which a single signal appears, which is fed to the first inputs of the elements 69.1.1 , 69.2.1, ..., 69.m.1 I. In re ultate due to the presence on both inputs 69.2.1 element and a positive pulse appears at its output a positive signal which passes through OR element 68.2.1 to an enable input of register 63.2.1 th and permits the emergence of the output code is stored therein. This code is fed to the first input of adder 59.2.1, at the second input of which there is an arc weight code of graph G. As a result of summing, the value from the output of adder 59.2.1 goes to the D-input of register 63.2.1, where it is saved. Thus, the next arc of graph G is fixed in fully connected MSs with bi-directional transmission of information.

Thus, the operation of the circuit occurs until an overflow signal appears at the output of the counter overflow 62. This situation will occur if an attempt is made to set the code of the number m in the counter 62. In this case, the overflow signal from the output of the counter 62 will go to the counter input of the counter 61. The counter 62 is set to zero. The counter 61 as a result of the arrival at its counting input of a single signal on a rising edge increases its value by one to a two code ("0.010").

Further, the operation of the circuit continues similarly to the principle described above until an overflow signal appears on the output of the counter overflow 61, indicating that the arcs of graph G are fixed in horizontal and vertical orientation. The remaining unsecured arcs must be assigned sequentially in a diagonal orientation. For example, in Fig. 4c, these are arcs fixed in modules 2-4, and then 5-7, etc. When all the arcs are assigned, and there are still arcs in the original column G for fixing, it is necessary to go to the next pair of columns, etc. After that, a similar operation is performed for modules MS 1-5, 4-8, 2-6 and 5-9, etc. for all arcs of the original graph. The overflow signal from the overflow output of the counter 61 goes to the R-input of the trigger 79, resetting it to the zero state. Then a zero signal will appear on its direct output, and a single signal on its inverse. A single signal from the inverse output of the RS-trigger 79 prohibition appears on the e-inputs of the counters 80, 81 and 82, allowing them to work.

The next clock pulse is fed to the first input of the 90 I element, to the counting input of the counter 62 and to the counting input of the counter 81. Since at the first input of the 89 And element and the second input of the 90 I element there is a zero potential from the direct output of the trigger 79, to their outputs the signal does not pass. At the output of the counter 71, the code does not appear, since at its input of the resolution the unit potential is not present. At the input of the counter 81, there is a unit potential from the direct output of the trigger 23. At the input of the resolution e of the counter 81 there is a unit potential from the inverse of the trigger 79, so its content along the rising edge is increased by one to code one ("0 ... 01"). The value of this code passes through the OR element 92 and is fed to the input of the decoder 65. Therefore, a single signal appears on its first output, which is fed to the first inputs of the elements 70.1.1, 70.1.2, ..., 70.1.n. At this time, the code of the number two from the output of the counter 80 passes through the OR element 78 and enters the input of the decoder 64. Therefore, a unit potential appears on its second output, which is fed to the second inputs of the elements 70.1.2, 70.2.2, ..., 70.m .2 I. Therefore, since there are single signals at the two inputs of element 70.1.2, a single potential appears at its output, which passes through element 68.1.2 OR and enters the enable input of the 63.1.2 register, allowing the appearance at its output the code stored in it. This code is fed to the first input of adder 59.1.2, at the second input of which there is a weight value of the fixed arc of graph G. As a result, the resulting amount is transferred to the D-input of register 63.1.2, where it is fixed. Thus, the first diagonal arc of graph G is fixed. For example, in Fig. 4c, it is an arc from module 4 to module 2 of the MS.

The next clock pulse is fed to the counter input of the counter 81 and since it is open, the value stored in it along the rising edge increases by one to a two code. This code passes through the OR element 92 and is fed to the input of the decoder 65, at the second output of which a single signal appears, which arrives at the first inputs of the elements 70.2.1, 70.2.2, ..., 70.2.n. At the second inputs of the elements 70.1.2, 70.2.2, ..., 70.m.2 And as before, there is a single signal from the second output of the decoder 64 (the code number two is stored in counter 80). Therefore, at the two inputs of the element 70.2.2 And there are single signals and therefore a unit appears at its output, which passes through the element 68.2.2 OR and is fed to the enable input of the 63.2.2 register. As a result of this, the code stored in it is fed to the first input of adder 59.2.2, at the second input of which there is the value of the arc weight of column G from the output of the main memory unit 10. The received amount is sent to the D-input of register 63.2.2 for recording. Thus, the next value of the weight of the arc in the diagonal orientation is recorded (in Fig. 4c this is the arc from module 7 to module 5 of the MS).

This continues until an attempt is made in counter 81 to set the code for the number m. This will cause the counter 81 to overflow, which will reset to zero. The overflow signal arrives at the counting input of the counter 80 and on the trailing edge increases its content by one, setting the number three code in it ("0 ... 011").

Similarly to the above, the next clock pulse is supplied to the counting input of the counter 81 and increases by one leading edge to the number one code. Further, the code recorded in the counter enters through the element 92 OR to the input of the decoder 65, at the first output of which there appears a unit arriving at the first inputs of the elements 70.1.1, 70.1.2, ..., 70.1.n. The code of the number three from the output of the counter 80 passes through the OR element 78 and is fed to the input of the decoder 64, at the third output of which a single signal appears, passing to the second inputs of the elements 70.1.3, 70.2.3, ..., 70.m.3. As a result, at the two inputs of the element 70.1.3 there are two unit signals and the unit from its output passes through the element 68.1.3 OR and enters the resolving input of the register 63.1.3. As a result, the code stored in it arrives at the first input of the adder 59.1.3. The received amount is sent to the D-input of the register 63.1.3 for recording. Thus, the next arc of the graph G is placed.

Thus, the operation of the device continues until the overflow signal appears on the output of the counter 80 (the stored code cannot be n + 1). In this case, the overflow signal from counter 80 enters its c-input counter 82 and enables the counting mode. The overflow signal from the output of the counter 80 also enters the r-input of the counter 81 and resets its contents to the unit code. The appearance of an overflow signal at the output of the counter 80 indicates that the first part of the diagonal arcs of column H of the MS is assigned, and the next step requires fixing the diagonal arcs, which in the MS have the direction “top-down-to-right” (Fig. -5, 4-8, 2-6, 5-9).

The next clock pulse is fed to the counting input of the counter 81 and on the rising edge increases its content by one to a two code ("0 ... 010"). The code of two from the output of the counter 81 enters through the element 92 OR to the input of the decoder 65, at the second output of which a single signal appears, which is fed to the first inputs of the elements 70.2.1, 70.2.2, ..., 70.2.n I. The value of the two from the output of the counter 82 through the element 78, OR enters the input of the decoder 64, at the second output of which a single signal appears, which is fed to the second inputs of the elements 70.1.2, 70.2.2, ..., 70.m.2 I. Thus, at the two inputs of the element 70.2 .2 And there is a single potential, which causes the appearance of a single signal at its output. This potential passes through OR element 68.2.2 and is fed to the ith input of register 63.2.2. As a result, the code stored in it appears, which is fed to the first input of the adder 59.2.2, at the second input of which there is the value of the weight of the arc to be fixed from the output of the RAM block 10. The total value goes to the D-input of register 63.2.2, where it is saved. Thus, the diagonal arc is fixed in the MS (in Fig. 4c it is an arc from module 1 to module 5).

The next clock pulse increases the contents of the counter 81 to a triple code on a rising edge. This code, through the OR element 92, is input to the decoder 65, at the third output of which a unit appears, which is fed to the first inputs of the elements 70.3.1, 70.3.2, ..., 70.3.n. At the second inputs of the elements 70.1.2, 70.2.2, ..., 70.m.2 And there is still a single potential. As a result, at the output of element 70.3.2 AND, a single signal appears that passes through element 68.3.2 OR to the input of register 63.3.2, at the output of which the code stored in it appears. This value goes to the first input of adder 59.3.2, at the second input of which there is a value of the arc weight of column G with the output of block 10 of RAM. As a result, the total value is fed to the D-input of register 63.3.2 for storage. Thus, the next diagonal arc of the graph G is fixed (in Fig. 4c, it is an arc from module 4 to module 8).

This continues until an overflow signal appears at the overflow output of counter 81. A single pulse from the overflow output of the counter 81 goes to the counting inputs of the counter 80 and 82. Since the counter 80 is closed, the code in it does not increase, and the counter 82 on the rising edge increases by one to a triple code. The counter 81 is reset to one.

The next clock pulse arrives at the counting input of the counter 81 and on the rising edge increases its contents to a two code. This code passes through the OR element 92 and is fed to the input of the decoder 65, at the second output of which a single pulse appears, which passes to the first inputs of the elements 70.2.1, 70.2.2, ..., 70.2.n I. At this time, the code is three s the output of the counter 82 passes through the OR element 78 and is fed to the input of the decoder 64, at the third output of which a single signal appears, which is fed to the second inputs of the elements 70.1.3, 70.2.3, ..., 70.m.3 I. As a result, the output of element 70.2.3 AND a single impulse is formed, which through element 68.2.3 OR is fed to the input of the nth input of register 63.2.3 and allows the appearance of the code stored in it. This code is fed to the first input of adder 59.2.3, at the second input of which there is a code for the weight of the arc of column G from the output of block 10 of RAM. The received amount goes to the D-input of register 63.2.3, where it is fixed. Thus, the next arc of the graph is fixed (in Fig. 4c it is the arc from module 2 to module 6 of the MS).

This continues until an overflow signal appears on the overflow output of the counter 82, which indicates an overflow of the counter 82, which is also a signal that the device is shutting down.

Thus, the proposed device is similar to the prototype allows you to generate the optimal placement of unweighted graphs in a linear topological model. It is possible to place weighted graphs in the device, and it is possible to select two models of the placement region - linear or circular. The found suboptimal arrangement is compared with the limiting variant by counting and comparing the bond lengths L and L ^∗ . Additionally, the proposed device allows you to search for lower estimates of placement in fully connected matrix systems with unidirectional information transfer according to the criterion of minimizing the intensity of the interaction of processes and data.

Claims (2)

1. A device for finding a lower estimate of placement in fully-connected matrix systems for unidirectional transmission of information, comprising a first shift register, a second shift register, a permutation generation unit (BFT), a permanent memory unit, a best option memory unit (BZLV), a switch, an ALU, a selection decoder arcs, reversible cell counter, RAM block, topology counter, first and second distance counters, multiplier, adder, register of minimum connection lengths, first comparison element, subtracter, start count trigger one, mode trigger, topology job trigger, link length register, second comparison element, arc counter, arc lock decoder, arc number register, minimum weight register, electronic graph model, group from the 1st to the n-th elements OR, group 1 on the mth element AND, the first and second elements AND, the second block of OR elements, the third element AND, the first and second one-shots, the first, second and third delay elements, the first block of OR elements, and the outputs of the BFP are connected to the corresponding inputs of the block read-only memory and corresponding in with BZLV odes, the signaling output of the BFP is connected to the installation input of the start trigger, the outputs of the permanent memory block are connected to the corresponding inputs of the switch, the output of which is connected to the input of the ALU, the output of which is connected to the information input of the BZLV, and the output of the BZLV is connected to the first information input of the ALU, output the overflow of the shift register is connected to the input of the shift register, the outputs of the first and second shift registers from the first to the n-th are connected to the first and second inputs of the elements OR of the 1st to the n-th respectively, the output is overflow The shift register is connected to the control input of the ALU and to the control input of the BFP, the device’s clock input is connected to the shift register input, to the BFP clock input and to the first inputs of the first and second elements AND, the output of the arc counter is connected to the input of the arc selection decoder and the register data input arc numbers, the output of the OR block of elements is connected to the first input of the comparison element and to the input of the minimum weight register, the output of the minimum weight register is connected to the second input of the comparison element and to the data input of the operational block memory, the output of the delay element is connected to the input of setting the minimum weight register and to the input of setting the register of the arc number, the output of the third element And is connected to the sync input of the minimum weight register and to the clock input of the register of the arc number, the output of the register of the arc number is connected to the information input of the arc lock decoder, output the overflow of the arc counter is connected to the enable input of the arc blocking decoder, as well as to the input of the delay element, the first counting input of the reversible cell counter and the recording input of the opera block memory, the output of the first element And is connected to the counting input of the arc counter and to the input of the delay element, the output of which is connected to the second input of the third element And, the first input of which is connected to the output of the comparison element, the second input of the first element And is connected to the direct output of the start trigger , which is also connected to the second input of the second element And, the third input of the first element And is connected to the inverse output of the mode trigger, the direct output of which is connected to the third input of the second element And, the output of the second element And It is connected to the second counting input of the reversible cell counter, the output of which is connected to the address input of the RAM block, the output of which is connected to the first input of the multiplier, the output of the distance counter is connected to the second input of the multiplier, the output of which is connected to the first input of the adder, the second input of which is connected to the output the register of the minimum length of links and to the second input of the subtracter, the adder output is connected to the data input of the register of the minimum length of links, the output of the delay element is connected to the clock input of the register m the minimum length of the links, the output of the second AND element and the counting input of the distance counter are connected to the input of the third delay element, the output of the second one-shot is connected to the sync input of the distance counter, the overflow output of which is connected to the counting inputs of the topology counter, distance counter and to the input of the second one-shot, the output of the topology counter connected to the input of the distance meter, the data input of the device is connected to the data input of the topology counter, the sync input of the topology counter is connected to the installation input of the device, etc. the pit output of the topology job trigger is connected to the enable input of the topology counter, the installation input of the topology job trigger is connected to the device setup input, the reset input of the topology job trigger is connected to the device setup input, the overflow counter overflow output is connected to the setup trigger mode input, the reset input of which is connected to the input of the installation of the device, the output of the register of the length of the connections is connected to the second input of the comparison element and to the first input of the subtractor, the first input of the element Avoniya is connected to the ALU output and the input of the link length register data, the output of a single vibrator is connected to the sync input of the link length register, the reset input of the start trigger counter is connected to the device setup input, the l-th output of the arc selection decoder (l = 1, 2, ..., m) connected to the lth input of the choice of the arc of the electronic graph model, the lth output of the arc lock decoder is connected to the lth input of the arc lock of the electronic graph model, the lth output of the weight of the arc of the electronic graph model is connected to the lth input of the block of OR elements and l-th input of the block of elements OR, l-th output of the element nta And the group of elements And from the 1st to the mth is connected to the l-th control input of the electronic model of the graph, the output of the block of OR elements is connected to the second information input of the ALU, the output of the comparison element is connected to the input of the first one-shot, the outputs of the elements from the 1st by the nth OR are connected to the corresponding inputs of the elements AND of the 1st by the mth, the output of the subtractor is connected to the output of the length of the device connections, characterized in that it additionally introduces a lower bound formation unit containing a matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders, the first and second row counters, the first and second column counter, the matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) registers, the first and second decoders of horizontally fixed arcs, the first and second decoders of vertically fixed arcs, a matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR elements, the first and second matrices of ij ( i = 1, 2, ..., m; j = 1, 2, ..., n) AND elements, the first OR element, the RS inhibit trigger, the second OR element, the third and fourth row counter, the third incident vertex counter, the first and second element And, and the input of the device is connected is connected to the S-input of the RS-inhibit trigger, the R-input of which is connected to the overflow output of the first column counter, the direct output of the RS-inhibit inhibit is connected to the second input of the second element And, as well as to the first input of the first element And, the inverse output of the RS trigger prohibition is connected to the e-inputs of the third and fourth row counter, as well as the e-input of the third counter of the incident vertex, the c-input of which is connected to the overflow output of the third row counter and to the r-input of the fourth row counter, the output of the third incident counter the top is connected to the overflow output of the device, the clock input of the device is connected to the counting input of the fourth row counter, the input of which is connected to the direct output of the mode trigger, the overflow output of the fourth row counter is connected to the counting input of the third row counter and the counting input of the third counter of the incident vertex, the first the input of the second OR element is connected to the output of the first line counter, the overflow output of which is connected to the counting input of the second line counter, the overflow output of which it is single with the enabling inputs of the first and second column counter, the overflow output of which is connected to the counting input of the first column counter, the counting input of the second column counter is connected to the device clock input, the output of the second column counter is connected to the input of the second decoder of vertically fixed arcs, the output of the first column counter is connected with the input of the first decoder of vertically fixed arcs, the th input of the first line counter is connected to the output of the first element And, the second input of which is connected to by the direct output of the mode trigger, the device’s clock input is connected to the first input of the second AND element, the output of which is connected to the counting input of the first line counter, the output of the third line counter is connected to the first input of the first OR element, the second input of which is connected to the output of the third counter of the incident vertex, the third the input of the first OR element is connected to the output of the second row counter, the output of the first OR element is connected to the input of the first decoder of horizontally fixed arcs, the outputs from the first to the nth of which are connected us with respective second inputs i.l groups, i.l, ..., i.l (i = 1, 2, ..., m) of the matrix elements of the second i.j (i = 1, 2, ..., m; j = 1, 2, ..., n) of AND elements, outputs from the first to the n-th second decoder of horizontally fixed arcs are connected to the corresponding first inputs of groups ij, ij, ..., ij (j = 1, 2, ..., n) of elements the second matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, the outputs from the first to the n-second second 67 decoder vertically fixed arcs connected to the corresponding second inputs of the groups lj, lj , ..., lj (j = 1, 2, ..., n) elements of the first matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, outputs from the first to n- The first decoder of vertically fixed arcs is connected to the corresponding the first inputs of groups 1.1, 2.1, ..., i.1 (i = 1, 2, ..., m) of the elements of the first matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, the output of elements ij (i = 1, 2, ..., m; j = 1, 2, ..., n) And the first matrix from ij (i = 1, 2, ..., m; j = 1, 2, ... , n) of elements And is connected to the first input of element ij (i = 1, 2, ..., m; j = 1, 2, ..., n) OR matrices from ij (i = 1, 2, ..., m; j = 1 , 2, ..., n) OR elements, the corresponding second inputs of which are connected to the outputs of the elements ij (i = 1, 2, ..., m; j = 1, 2, ..., n) And the second matrix of ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements And, the outputs of the elements ij (i = 1, 2, ... , m; j = 1, 2, ..., n) OR matrices from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) elements OR are connected to the corresponding permitting inputs of the matrix from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) of registers whose outputs are connected to the corresponding first ij (i = 1, 2, ..., m; j = 1, 2, ..., n ) inputs of matrix elements from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders, to the second inputs of which the output of the RAM block is connected, outputs of elements ij (i = 1, 2, ... , m; j = 1, 2, ..., n) matrices from ij (i = 1, 2, ..., m; j = 1, 2, ..., n) adders are connected to the corresponding etstvuyuschim D-inputs of matrix i.j (i = 1, 2, ..., m; j = 1, 2, ..., n) of registers, the output of the fourth line counter 81 are connected to third input of the second OR element 92. 2. The device according to claim 1, characterized in that the electronic model of the graph contains m electronic models of the arc, and the l-th electronic model of the arc (l = 1, 2, ..., m) contains an arc lock trigger, an arc weight register, a lock register arcs, the first element AND, the second element AND, the OR element, and the inputs of the first element AND are connected to the corresponding inputs of the job graph of the device, the output of the first element And is connected to the sync input of the arc weight register and to the installation input of the arc lock trigger, the reset input of which is connected to l arc lock input an electronic graph model, the input of the arc weight register data is connected to the l-th input of the device's arc weight, the first input of the OR element is connected to the l-th control input of the electronic model of the graph, and the second input of the OR element is connected to the output of the second And element, the first input of which is connected with the direct output of the arc lock trigger and with the enable input of the arc lock register, the second input of the second element AND is connected to the l-th input of the choice of the arc of the electronic model of the graph, the reset input of the arc lock register is connected to the l-th input of the device reset, output the arc lock register is connected to the l-th output of the arc weight of the graph's electronic model, which is also connected to the output of the arc weight register, the output of the OR element is connected to the enable input of the arc weight register.

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